JAJSFF6B june 2018 – september 2020 DS90C189-Q1
PRODUCTION DATA
The DS90C189-Q1 has several features to assist with managing power consumption. The device can be configured through the MODE0 control pin to enable only the required number of LVDS drivers for each application. If no clock is applied to the IN_CLK pin, the DS90C189-Q1 will enter a low power state. To place the DS90C189-Q1 in its lowest power state, the device can be powered down by driving the PDB pin to LOW.