DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz
- SNLS043H May 2000 – January 2016 DS90CR216A , DS90CR286A , DS90CR286A-Q1
  
  PRODUCTION DATA.

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DATA SHEET

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features

20 to 66 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Best–in–Class Set and Hold Times on Rx Outputs
Rx Power Consumption < 270 mW (Typ) at 66 MHz Worst Case
Rx Power-Down Mode < 200 μW (Max)
ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Pin or 48-Pin DGG (TSSOP) Package
Operating Temperature: −40°C to 85°C
Automotive Q Grade Available - AEC-Q100 Grade 3 Qualified

2 Applications

Video Displays
Automotive Infotainment
Industrial Printers and Imaging
Digital Video Transport
Machine Vision

3 Description

The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.

The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DS90CR286AMTD	TSSOP (56)	14.00 mm x 6.10 mm
DS90CR286AQMT	TSSOP (56)	14.00 mm x 6.10 mm
DS90CR216AMTD	TSSOP (48)	12.50 mm × 6.10 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Block Diagram (DS90CR216A)

DS90CR216A DS90CR286A DS90CR286A-Q1 216_typ_blk_diagram.gif

4 Revision History

Changes from G Revision (August 2015) to H Revision

Changed Figure 6 and Figure 7 to clarify that TxIN on Tx is the same as RxOUT on Rx Go
Changed "limit output amplitude" to "reduce reflections from long board traces" for clarificationGo
Deleted 0.01-µF and 0.001-µF caps from required DC power supply coupling capacitorsGo
Deleted "Setup and Hold Time" label from the Rx strobe window diagram to clarify RSKM conceptGo
Changed direction of Rx strobe position shift for correct left and right RSKM margin shift behaviorGo
Added new Application Note reference for RSKM improvementGo
Added improved layout guidelinesGo
Changed Figure 28 graphic to clarify the use of series resistors on LVCMOS output Go

Changes from F Revision (February 2013) to G Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Changed specification title to clarify 3.3 V LVCMOS and not standard 5 V CMOSGo
Changed title and graphic of figure to clarify 3.3 V LVCMOS and not standard 5 V CMOSGo
Changed title of DS90CR286A mapping to clarify the make-up of the LVDS linesGo
Changed title of DS90CR216A mapping to clarify the make-up of the LVDS linesGo
Added cycle-to-cycle jitter value of 250 ps instead of TBD psGo

Changes from E Revision (February 2013) to F Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

DGG Package

56-Pin TSSOP

DS90CR286A Top View

DS90CR216A DS90CR286A DS90CR286A-Q1 01291022.png

DGG Package

48-Pin TSSOP

DS90CR216A Top View

DS90CR216A DS90CR286A DS90CR286A-Q1 10087313.png

DS90CR286A Pin Functions — DGG0056A Package — 28-Bit Channel Link Receiver

PIN		I/O , TYPE	PIN DESCRIPTION
NAME	NO.	I/O , TYPE	PIN DESCRIPTION
RxIN0+, RxIN0-, RxIN1+, RxIN1-, RxIN2+, RxIN2-, RxIN3+, RxIN3-	10, 9, 12, 11, 16, 15, 20, 19	I, LVDS	Positive and negative LVDS differential data inputs. 100-Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxCLKIN+, RxCLKIN-	18, 17	I, LVDS	Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxOUT[27:0]	7, 6, 5, 3, 2, 1, 55, 54, 53, 51, 50, 49, 47, 46, 45, 43, 42, 41, 39, 38, 37, 35, 34, 33, 32, 30, 29, 27	O, LVCMOS	LVCMOS level data outputs.
RxCLK OUT	26	O, LVCMOS	LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN	25	I, LVCMOS	LVCMOS level input. When asserted low, the receiver outputs are low.
V_CC	56, 48, 40, 31	Power	Power supply pins for LVCMOS outputs.
GND	52, 44, 36, 28, 4	Power	Ground pins for LVCMOS outputs.
PLL V_CC	23	Power	Power supply for PLL.
PLL GND	24, 22	Power	Ground pin for PLL.
LVDS V_CC	13	Power	Power supply pin for LVDS inputs.
LVDS GND	21, 14, 8	Power	Ground pins for LVDS inputs.

DS90CR216A Pin Functions — DGG0048A Package — 21-Bit Channel Link Receiver

PIN		I/O , TYPE	PIN DESCRIPTION
NAME	NO.	I/O , TYPE	PIN DESCRIPTION
RxIN0+, RxIN0-, RxIN1+, RxIN1-, RxIN2+, RxIN2-	9, 8, 11, 10, 15, 14	I, LVDS	Positive and negative LVDS differential data inputs. 100-Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxCLKIN+, RxCLKIN-	17, 16	I, LVDS	Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxOUT[20:0]	5, 4, 2, 1, 47, 46, 45, 43, 41, 40, 39, 37, 35, 34, 33, 31, 30, 29, 27, 26, 24	O, LVCMOS	LVCMOS level data outputs.
RxCLK OUT	23	O, LVCMOS	LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN	22	I, LVCMOS	LVCMOS level input. When asserted low, the receiver outputs are low.
V_CC	48, 42, 36, 28	Power	Power supply pins for LVCMOS outputs.
GND	44, 38, 32, 25, 3	Power	Ground pins for LVCMOS outputs.
PLL V_CC	20	Power	Power supply for PLL.
PLL GND	21, 19	Power	Ground pin for PLL.
LVDS V_CC	12	Power	Power supply pin for LVDS inputs.
LVDS GND	18, 13, 7	Power	Ground pins for LVDS inputs.

6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply voltage (V_CC)	–0.3	4	V
LVCMOS output voltage	–0.3	(V_CC + 0.3 V)	V
LVDS receiver input voltage	–0.3	(V_CC + 0.3 V)	V
Junction temperature		150	°C
Lead temperature (soldering, 4 sec)		260	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±7000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±700	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

	MIN	NOM	MAX	UNIT
Supply voltage (V_CC)	3.0	3.3	3.6	V
Operating free air temperature (T_A)	–40	25	85	°C
Receiver input range	0		2.4	V
Supply noise voltage (V_NOISE)			100	mV_PP

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90CR286A/-Q1	DS90CR216A	UNIT
		DGG (TSSOP)	DGG (TSSOP)
		56 PINS	48 PINS
R_θJA	Junction-to-ambient thermal resistance	64.6	67.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	20.6	22.1	°C/W
R_θJB	Junction-to-board thermal resistance	33.3	34.8	°C/W
ψ_JT	Junction-to-top characterization parameter	1.0	1.1	°C/W
ψ_JB	Junction-to-board characterization parameter	33.0	34.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
LVCMOS DC SPECIFICATIONS (For PWR DWN Pin)
V_IH	High Level Input Voltage			2		V_CC	V
V_IL	Low Level Input Voltage			GND		0.8	V
V_CL	Input Clamp Voltage	I_CL = −18 mA			–0.79	–1.5	V
I_IN	Input Current	V_IN = 0.4 V, 2.5 V or V_CC			1.8	10	μA
I_IN	Input Current	V_IN = GND		–10	0		μA
LVCMOS DC SPECIFICATIONS
V_OH	High Level Output Voltage	I_OH = −0.4 mA		2.7	3.3		V
V_OL	Low Level Output Voltage	I_OL = 2 mA			0.06	0.3	V
I_OS	Output Short Circuit Current	V_OUT = 0 V			–60	–120	mA
LVDS RECEIVER DC SPECIFICATIONS
V_TH	Differential Input High Threshold	V_CM = +1.2V				100	mV
V_TL	Differential Input Low Threshold			–100			mV
I_IN	Input Current	V_IN = +2.4V, V_CC = 3.6V				±10	μA
I_IN	Input Current	V_IN = 0V, V_CC = 3.6V				±10	μA
RECEIVER SUPPLY CURRENT
ICCRW	Receiver Supply Current Worst Case	C_L = 8 pF, Worst Case Pattern, DS90CR286A (Figure 1 Figure 2), T_A=−10°C to +70°C	f = 33 MHz		49	65	mA
			f = 37.5 MHz		53	70	mA
			f = 66 MHz		81	105	mA
ICCRW	Receiver Supply Current Worst Case	C_L = 8 pF, Worst Case Pattern, DS90CR286A (Figure 1 Figure 2), T_A=−40°C to +85°C	f = 40 MHz		53	70	mA
ICCRW	Receiver Supply Current Worst Case		f = 66 MHz		81	105	mA
ICCRW	Receiver Supply Current Worst Case	C_L = 8 pF, Worst Case Pattern, DS90CR216A (Figure 1 Figure 2), T_A=−10°C to +70°C	f = 33 MHz		49	55	mA
			f = 37.5 MHz		53	60	mA
			f = 66 MHz		78	90	mA
ICCRW	Receiver Supply Current Worst Case	C_L = 8 pF, Worst Case Pattern, DS90CR216A (Figure 1 Figure 2), T_A=−40°C to +85°C	f = 40 MHz		53	60	mA
ICCRW	Receiver Supply Current Worst Case		f = 66 MHz		78	90	mA
ICCRZ	Receiver Supply Current Power Down	Power Down = Low Receiver Outputs Stay Low during Power Down Mode			10	55	μA

(1) Typical values are given for V_CC = 3.3 V and T_A = 25ºC.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except V_OD and ΔV_OD).

6.6 Switching Characteristics: Receiver

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER			MIN	TYP	MAX	UNIT
CLHT	LVCMOS Low-to-High Transition Time (Figure 2)			2	5	ns
CHLT	LVCMOS High-to-Low Transition Time (Figure 2)			1.8	5	ns
RSPos0	Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10)	f = 40 MHz	1	1.4	2.15	ns
RSPos1	Receiver Input Strobe Position for Bit 1		4.5	5	5.8	ns
RSPos2	Receiver Input Strobe Position for Bit 2		8.1	8.5	9.15	ns
RSPos3	Receiver Input Strobe Position for Bit 3		11.6	11.9	12.6	ns
RSPos4	Receiver Input Strobe Position for Bit 4		15.1	15.6	16.3	ns
RSPos5	Receiver Input Strobe Position for Bit 5		18.8	19.2	19.9	ns
RSPos6	Receiver Input Strobe Position for Bit 6		22.5	22.9	23.6	ns
RSPos0	Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10)	f = 66 MHz	0.7	1.1	1.4	ns
RSPos1	Receiver Input Strobe Position for Bit 1		2.9	3.3	3.6	ns
RSPos2	Receiver Input Strobe Position for Bit 2		5.1	5.5	5.8	ns
RSPos3	Receiver Input Strobe Position for Bit 3		7.3	7.7	8	ns
RSPos4	Receiver Input Strobe Position for Bit 4		9.5	9.9	10.2	ns
RSPos5	Receiver Input Strobe Position for Bit 5		11.7	12.1	12.4	ns
RSPos6	Receiver Input Strobe Position for Bit 6		13.9	14.3	14.6	ns
RSKM	RxIN Skew Margin⁽²⁾ (Figure 11)	f = 40 MHz	490			ps
RSKM	RxIN Skew Margin⁽²⁾ (Figure 11)	f = 66 MHz	400			ps
RCOP	RxCLK OUT Period (Figure 3)		15	T	50	ns
RCOH	RxCLK OUT High Time (Figure 3)	f = 40 MHz	10	12.2		ns
RCOL	RxCLK OUT Low Time (Figure 3)		10	11		ns
RSRC	RxOUT Setup to RxCLK OUT (Figure 3)		6.5	11.6		ns
RHRC	RxOUT Hold to RxCLK OUT (Figure 3)		6	11.6		ns
RCOH	RxCLK OUT High Time (Figure 3)	f = 66 MHz	5	7.6		ns
RCOL	RxCLK OUT Low Time (Figure 3)		5	6.3		ns
RSRC	RxOUT Setup to RxCLK OUT (Figure 3)		4.5	7.3		ns
RHRC	RxOUT Hold to RxCLK OUT (Figure 3)		4	6.3		ns
RCCD	RxCLK IN to RxCLK OUT Delay at 25°C, V_CC = 3.3 V⁽³⁾ (Figure 4)		3.5	5	7.5	ns
RPLLS	Receiver Phase Lock Loop Set (Figure 5)				10	ms
RPDD	Receiver Power Down Delay (Figure 8)				1	μs

(1) Typical Values are given for V_CC = 3.3 V and T_A = 25ºC

(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).

(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the DS90CR215/DS90CR285 transmitter and DS90CR216A/DS90CR286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.

DS90CR216A DS90CR286A DS90CR286A-Q1 10087302.png

Figure 1. “Worst Case” Test Pattern

DS90CR216A DS90CR286A DS90CR286A-Q1 10087304.gif

Figure 2. LVCMOS Output Load and Transition Times

DS90CR216A DS90CR286A DS90CR286A-Q1 10087305.png

Figure 3. Setup/Hold and High/Low Times

DS90CR216A DS90CR286A DS90CR286A-Q1 10087306.png

Figure 4. Clock In to Clock Out Delay

DS90CR216A DS90CR286A DS90CR286A-Q1 10087307.png

Figure 5. Phase Lock Loop Set Time

DS90CR216A DS90CR286A DS90CR286A-Q1 10087309.gif

Figure 6. DS90CR286A Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialized Data

DS90CR216A DS90CR286A DS90CR286A-Q1 10087310.gif

Figure 7. DS90CR216A Mapping of 21 LVCMOS Parallel Data to 3D + C LVDS Serialized Data

DS90CR216A DS90CR286A DS90CR286A-Q1 10087308.png

Figure 8. Power Down Delay

DS90CR216A DS90CR286A DS90CR286A-Q1 10087325.png

Figure 9. DS90CR286A LVDS Input Strobe Position

DS90CR216A DS90CR286A DS90CR286A-Q1 10087326.png

Figure 10. DS90CR216A LVDS Input Strobe Position

DS90CR216A DS90CR286A DS90CR286A-Q1 10087311.png

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max

Tppos—Transmitter output pulse position (min and max)

Cable Skew—typically 10 ps–40 ps per foot, media dependent

RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)⁽¹⁾ + ISI (Inter-symbol interference)⁽²⁾

1. Cycle-to-cycle jitter depends on the Tx source. if a Channel Link I Source Transmitter is used, clock jitter is maintained to less than 250 ps at 66 MHz.

2. ISI is dependent on interconnect length; may be zero.

Figure 11. Receiver LVDS Input Skew Margin

6.7 Typical Characteristics

DS90CR216A DS90CR286A DS90CR286A-Q1 Typ_RxOUT_v_RxCLKOUT_66_MHz.gif

Figure 12. Parallel PRBS-7 on LVCMOS Outputs at 66 MHz

DS90CR216A DS90CR286A DS90CR286A-Q1 RxOUT_Setup_to_RxCLKOUT_Time_66_MHz.gif

Figure 14. Typical RxOUT Setup Time at 66 MHz
(RSRC = 7.1 ns)

DS90CR216A DS90CR286A DS90CR286A-Q1 Typ_RxOUT_Strobe_66_MHz.gif

Figure 13. Typical RxOUT Strobe Position at 66 MHz

DS90CR216A DS90CR286A DS90CR286A-Q1 RxOUT_Hold_to_RxCLKOUT_Time_66_MHz.gif

Figure 15. Typical RxOUT Hold Time at 66 MHz
(RHRC = 7.0 ns)