JAJSGI8D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 8.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 8.8 Deserializer Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Timing Diagrams and Test Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Frame Format
      2. 10.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 10.3.3  Deserializer Multiplexer Input
      4. 10.3.4  Error Detection
      5. 10.3.5  Synchronizing Multiple Cameras
      6. 10.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 10.3.7  LVCMOS VDDIO Option
      8. 10.3.8  EMI Reduction
        1. 10.3.8.1 Deserializer Staggered Output
        2. 10.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 10.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 10.3.10 Power Down
    4. 10.4 Device Functional Modes
      1. 10.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 10.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 10.4.3 MODE Pin on Deserializer
      4. 10.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 10.4.5 Built-In Self Test
      6. 10.4.6 BIST Configuration and Status
      7. 10.4.7 Sample BIST Sequence
    5. 10.5 Programming
      1. 10.5.1 Programmable Controller
      2. 10.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 10.5.3 I2C Pass-Through
      4. 10.5.4 Slave Clock Stretching
      5. 10.5.5 ID[x] Address Decoder on the Deserializer
      6. 10.5.6 Multiple Device Addressing
    6. 10.6 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Power Over Coax
      2. 11.1.2 Power-Up Requirements and PDB Pin
      3. 11.1.3 AC Coupling
      4. 11.1.4 Transmission Media
      5. 11.1.5 Adaptive Equalizer – Loss Compensation
    2. 11.2 Typical Applications
      1. 11.2.1 Coax Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 STP Application
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Interconnect Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from C Revision (November 2018) to D Revision

  • Added tDLH and tDHL to Output Load and Transition Times diagramGo
  • Added 953A in the list of compatible serializersGo
  • Changed text in MODE Pin Configuration figure from "Serializer" to "Deserializer"Go
  • Clarified bit descriptions for registers 0x1D-0x1E bits 4 and 0Go
  • Added timing diagram and data table for PDB to I2C ready delayGo

Changes from B Revision (October 2016) to C Revision

  • Clarified when PCLK becomes active with respect to LOCK Go
  • Added Power Over Coax supply noise to the recommended operating conditions table Go
  • Corrected to tDLH and tDHL for data low-to-high and high-to-low transition time Go
  • Moved the timing diagrams to the Parameter Measurement Information sectionGo
  • Added reference to compatibility with DS90UB953-Q1/935-Q1 serializers Go
  • Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram Go
  • Updated register "TYPE" column per legend Go
  • Added type and default value to the reserved register bits that were missing this information Go

Changes from A Revision (June 2016) to B Revision

  • Added Back Channel Line Rate specification; also added footnote for clarification between MHz and Mbps distinction.Go
  • Revised back channel VOD specification from 175mV to 182 mV. Go
  • Removed 'ns' unit from specifications referencing period in units of T.Go
  • Revise Deserializer Delay specification due to the swapped information. Go
  • Revised jitter tolerance curve to be for typical system IJT configuration with DS90UB913A linked to DS90UB914A. Go
  • Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. Go
  • Fixed typo and changed "deserializer" to "serializer".Go
  • Added register 0x05 for Forward Channel Low Frequency Gain. Go
  • Added registers 0x27, 0x47 for Forward Channel Tuning/Impedance Control.Go
  • Revised rise time and delay conditions to include 10% to 90% parameters instead of VIH and VIL.Go
  • Changed max rise time for VDDIO and VDD_N to be 5ms instead of 1.5ms during power-up. Go
  • Revised power-up timing paragraph for clarity and correctness.Go
  • Changed VIL and VIH specs to 10% and 90% respectively for rising/falling edges.Go

Changes from * Revision (April 2016) to A Revision

  • ドキュメントを、DS90UB913A-Q1 SNLS443とDS90UB914A-Q1 SNLS499の2つに分割Go
  • 改訂履歴を、このドキュメントがDS90UB913A-Q1 SNLS443データシートの一部であったときの変更部分も含めるよう結合Go
  • Added 車載用機能Go
  • Updated pin description for ROUT to include active/inactive outputs corresponding to MODE setting.Go
  • Added pin description to GPIO pins to leave open if unused. Go
  • Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. Go
  • Added pin description to RIN pins to leave open if unused. Go
  • Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. Go
  • Added additional thermal characteristics.Go
  • Added GPIO[3:0] typical pin capacitance Go
  • Changed Differential Input Voltage minimum specification.Go
  • Changed Single-Ended Input Voltage minimum specification.Go
  • Added Back Channel Differential Output Voltage minimum specification.Go
  • Added Back Channel Single-Ended Output Voltage minimum specification.Go
  • Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI scales with PCLK frequency.” Also added below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x 28 ) 12-bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) Go
  • Updated IDDIOR for VDDIO=1.89V, CL=8pF, Worst-Case Pattern with f=50 MHz, 12-bit low freq mode to typical value of 16 mA; value is currently 21 mA. Go
  • Updated IDDIOR for VDDIO=1.89V, CL=8pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 10 mA; value is currently 14 mA.Go
  • Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=100 MHz, 10-bit mode to typical value of 69 mA; value is currently 57 mA. Go
  • Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=75 MHz, 12-bit high freq mode to typical value of 71 mA; value is currently 60 mA.Go
  • Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 67 mA; value is currently 56 mA.Go
  • Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDDIO voltage.Go
  • Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote and nominal clock period to be in terms of 'T'.Go
  • Changed typo on footnote to reflect 'tDPJ'.Go
  • Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’ Go
  • Updated Figure 3 “Deserializer Vswing Diagram” with correct notation. Go
  • Changed Figure 3 to clarify difference between STP and CoaxGo
  • Table 2, row 5 with “static” input LOCK output status changed to “L”. Go
  • Table 5 heading updated to state “DS90UB914A-Q1 DESERIALIZER. Go
  • Changed description of deserializer reg 0x00 bit[0]=0 from "set using address coming from CAD" to "set from ID[x]" .Go
  • Added row to register 0x01[2] for Back Channel Enable – 0: Disable 1: Enable.Go
  • Changed SSCG Units for fmod (register 0x02[3:0]) to Reflect Hz instead of KHz.Go
  • Changed parity error reset bit to be NOT self-clearing. Go
  • Changed EQ gain values (dB) @ maximum line rate (1.4Gbps).Go
  • Changed description of deserializer reg 0x04 to have correct register setting for each equalization gain level.Go
  • Added registers 0x26, 0x46 for Bidirectional Control Channel (BCC)Tuning. Go
  • Added deserializer 0x4C SEL register.Go
  • Updated EQ Register Bits 0x4E[3:0] to be Reserved. Also changed EQ gain values (dB) @ maximum line rate (1.4Gbps).Go
  • Added reference to Power over Coax Application reportGo
  • Updated power up sequencing information and timing diagram. Go
  • Added power up sequencing information and timing diagram.Go
  • Added 914A PDB Reset timing constraints and diagram. Go
  • Removed Figure 21 and Figure 43 regarding adaptive equalizer graphs for loss compensation (Coax/STP). Go
  • Renamed C1 and C2 to C22 and C23 for RIN0+ and RIN0- respectively on Typical Application Diagrams (Coax & STP). Go
  • Added description specifying that the voltage applied on VDDIO (1.8 V, 3.3 V) or VDD_n (1.8 V) should be at the input pin – any board level DC drop should be compensated. Go
  • Added 914A EVM layout example image. Go