Figure 7-1 shows a typical application of the DS90UR241 Serializer (SER). The LVDS outputs use a 100Ω termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins. At a minimum, three 0.1uF capacitors must be used for local bypassing. A system GPO (General Purpose Output) controls the TPWDNB pin. In this application the TRFB pin is tied High to latch data on the rising edge of the TCLK. The DEN signal is not used and is tied High also. The application is to the companion Deserializer (DS90UR124) so the RAOFF pin is tied low to scramble the data and improve link signal quality. In this application the link is typical, therefore the VODSEL pin is tied Low for the standard LVDS swing. The pre-emphasis input uses a resistor to ground to set the amount of pre-emphasis desired by the application.

Figure 7-5 shows a typical application of the DS90UR124 Deserializer (DES). The LVDS inputs use a 100Ω termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1uF capacitors must be used for local bypassing. A system GPO (general-purpose output) controls the RPWDNB pin. In this application the RRFB pin is tied High to strobe the data on the rising edge of the RCLK. The REN signal is not used and is tied High also. The application is to the companion Serializer (DS90UR241) so the RAOFF pin is tied low to descramble the data. Output (LVCMOS) signal quality is set by the SLEW pin, and the PTOSEL pin can be used to reduce simultaneous output switching by introducing a small amount of delay between output banks.