To assist vendors with test verification, the DS90UR241 and DS90UR124 is equipped with built-in self-test (BIST) capability to support both system manufacturing and field diagnostics. BIST mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized and expensive test equipment. This feature provides a simple method for a system host to perform diagnostic testing of both Serializer and Deserializer. The BIST function is easily configured through the 2 control pins on the DS90UR124. When the BIST mode is activated, the Serializer has the ability to transfer an internally generated PRBS data pattern. This pattern traverses across interconnecting links to the Deserializer. The DS90UR124 includes an on-chip PRBS pattern verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins on the Deserializer.

The @SPEED-BIST feature uses 2 signal pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH) activates the test feature on the Deserializer. After the BIST mode is enabled, all the data input channels DIN[23:0] on the DS90UR241 Serializer must be set logic LOW or floating in order for Deserializer to start accepting data. An input clock signal (TCLK) for the Serializer must also be applied during the entire BIST operation. The BISTM pin selects error reporting status mode of the BIST function. When BIST is configured in the error status mode (BISTM = LOW), each of the ROUT[23:0] outputs correspond to bit errors on a cycle-by-cycle basis. The result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0] data output pins. In the BIST error-count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is used to represent the number of errors detected (0 to 255 max). The successful completion of the BIST test is reported on the PASS pin on the Deserializer. The Deserializer's PLL must first be locked to make sure the PASS status is valid. The PASS status pin stay LOW and then transition to HIGH once a BER of 1x10^-9 is achieved across the transmission link.