SNLS231P September   2006  – August 2024 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Serializer Input Timing Requirements for TCLK
    7. 5.7 Serializer Switching Characteristics
    8. 5.8 Deserializer Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Initialization and Locking Mechanism
      2. 6.3.2  Data Transfer
      3. 6.3.3  Resynchronization
      4. 6.3.4  Powerdown
      5. 6.3.5  Tri-State
      6. 6.3.6  Pre-Emphasis
      7. 6.3.7  AC-Coupling and Termination
        1. 6.3.7.1 Receiver Termination Option 1
        2. 6.3.7.2 Receiver Termination Option 2
        3. 6.3.7.3 Receiver Termination Option 3
      8. 6.3.8  Signal Quality Enhancers
      9. 6.3.9  @SPEED-BIST Test Feature
      10. 6.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Using the DS90UR241 and DS90UR124
      2. 7.1.2 Display Application
      3. 7.1.3 Typical Application Connection
    2. 7.2 Typical Applications
      1. 7.2.1 DS90UR241-Q1 Typical Application Connection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Power Considerations
          2. 7.2.1.2.2 Noise Margin
          3. 7.2.1.2.3 Transmission Media
          4. 7.2.1.2.4 46
          5. 7.2.1.2.5 Live Link Insertion
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DS90UR124 Typical Application Connection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Power System Considerations
        2. 7.4.1.2 LVDS Interconnect Guidelines
      2. 7.4.2 Layout Examples
  9. 7Device and Documentation Support
    1. 7.1 Device Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  10. 8Revision History
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

5.8 Deserializer Switching Characteristics

over recommended operating supply and temperature ranges unless otherwise specified
PARAMETERTEST CONDITIONSPIN/FREQ.MINTYPMAXUNIT
tRCPReceiver out Clock PeriodtRCP = tTCP,
PTOSEL = H		RCLK
Figure 5-15		23.25T200ns
tRDCRCLK Duty CyclePTOSEL = H,
SLEW = L		45%50%55%
tCLHLVCMOS Low-to-High Transition TimeCL = 4pF
(lumped load),
SLEW = H		ROUT [0:23],
RCLK, LOCK		1.52.5ns
tCHLLVCMOS High-to-Low Transition Time1.52.5ns
tCLHLVCMOS Low-to-High Transition TimeCL = 4pF
(lumped load),
SLEW = L		ROUT [0:23],
RCLK, LOCK		2.03.5ns
tCHLLVCMOS High-to-Low Transition Time2.03.5ns
tROSROUT (0:7) Setup Data to RCLK (Group 1)PTOSEL = L,
SLEW = H,
Figure 5-16		ROUT[0:7](0.35)× tRCP(0.5×tRCP)–3 UIns
tROHROUT (0:7) Hold Data to RCLK (Group 1)(0.35)× tRCP(0.5×tRCP)–3 UIns
tROSROUT (8:15) Setup Data to RCLK (Group 2)PTOSEL = L,
SLEW = H,
Figure 5-16		ROUT [8:15], LOCK(0.35)× tRCP(0.5×tRCP)–3 UIns
tROHROUT (8:15) Hold Data to RCLK (Group 2)(0.35)× tRCP(0.5×tRCP)–3 UIns
tROSROUT (16:23) Setup Data to RCLK (Group 3)ROUT [16:23](0.35)× tRCP(0.5×tRCP)–3 UIns
tROHROUT (16:23) Setup Data to RCLK (Group 3)(0.35)× tRCP(0.5×tRCP)–3 UIns
tROSROUT (0:7) Setup Data to RCLK (Group 1)PTOSEL = H,
SLEW = H,
Figure 5-15		ROUT[0:7](0.35)× tRCP(0.5×tRCP)–2 UIns
tROHROUT (0:7) Hold Data to RCLK (Group 1)(0.35)× tRCP(0.5×tRCP)+2 UIns
tROSROUT (8:15) Setup Data to RCLK (Group 2)ROUT [8:15], LOCK(0.35)× tRCP(0.5×tRCP)−1 UIns
tROHROUT (8:15) Hold Data to RCLK (Group 2)(0.35)× tRCP(0.5×tRCP)+1 UIns
tROSROUT (16:23) Setup Data to RCLK (Group 3)ROUT [16:23](0.35)× tRCP(0.5×tRCP)+1 UIns
tROHROUT (16:23) Setup Data to RCLK (Group 3)(0.35)× tRCP(0.5×tRCP)–1 UIns
tHZRHIGH to Tri-state DelayPTOSEL = H,
Figure 5-14		ROUT [0:23],
RCLK, LOCK		310ns
tLZRLOW to Tri-state Delay310ns
tZHRTri-state to HIGH Delay310ns
tZLRTri-state to LOW Delay310ns
tDDDeserializer DelayPTOSEL = H,
Figure 5-12		RCLK[5+(5/56)]T+3.7[5+(5/56)]T +8ns
tDSRDeserializer PLL Lock Time from PowerdownSee Figure 5-145MHz128k*Tms
43MHz128k*T
RxIN_TOL-LReceiver INput TOLerance LeftSee
Figure 5-17		5MHz–43MHz0.25UI
RxIN_TOL-RReceiver INput TOLerance RightSee
Figure 5-17		5MHz–43MHz0.25UI
DS90UR124-Q1 DS90UR241-Q1 Serializer Input Checkerboard PatternFigure 5-1 Serializer Input Checkerboard Pattern
DS90UR124-Q1 DS90UR241-Q1 Deserializer Output Checkerboard PatternFigure 5-2 Deserializer Output Checkerboard Pattern
DS90UR124-Q1 DS90UR241-Q1 Serializer LVDS Output Load and Transition TimesFigure 5-3 Serializer LVDS Output Load and Transition Times
DS90UR124-Q1 DS90UR241-Q1 Serializer Input Clock Transition TimesFigure 5-4 Serializer Input Clock Transition Times
DS90UR124-Q1 DS90UR241-Q1 Serializer Setup and Hold TimesFigure 5-5 Serializer Setup and Hold Times
DS90UR124-Q1 DS90UR241-Q1 Serializer Tri-State Test Circuit and DelayFigure 5-6 Serializer Tri-State Test Circuit and Delay
DS90UR124-Q1 DS90UR241-Q1 Serializer PLL Lock Time, and TPWDNB Tri-State DelaysFigure 5-7 Serializer PLL Lock Time, and TPWDNB Tri-State Delays
DS90UR124-Q1 DS90UR241-Q1 Serializer DelayFigure 5-8 Serializer Delay
DS90UR124-Q1 DS90UR241-Q1 Transmitter Output Eye Opening (TxOUT_E_O)Figure 5-9 Transmitter Output Eye Opening (TxOUT_E_O)
DS90UR124-Q1 DS90UR241-Q1 Serializer VOD Diagram
VOD = (DOUT+) – (DOUT−)
Differential output signal is shown as (DOUT+) – (DOUT−), device in Data Transfer mode.
Figure 5-10 Serializer VOD Diagram
DS90UR124-Q1 DS90UR241-Q1 Deserializer LVCMOS Output Load and Transition TimesFigure 5-11 Deserializer LVCMOS Output Load and Transition Times
DS90UR124-Q1 DS90UR241-Q1 Deserializer DelayFigure 5-12 Deserializer Delay
DS90UR124-Q1 DS90UR241-Q1 Deserializer Tri-State Test Circuit and TimingFigure 5-13 Deserializer Tri-State Test Circuit and Timing
DS90UR124-Q1 DS90UR241-Q1 Deserializer PLL Lock Times and RPWDNB Tri-State DelayFigure 5-14 Deserializer PLL Lock Times and RPWDNB Tri-State Delay
DS90UR124-Q1 DS90UR241-Q1 Deserializer Setup and Hold Times and PTO, PTOSEL = HFigure 5-15 Deserializer Setup and Hold Times and PTO, PTOSEL = H
DS90UR124-Q1 DS90UR241-Q1 Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI).
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI).
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI).
Figure 5-16 Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
DS90UR124-Q1 DS90UR241-Q1 Receiver Input Tolerance (RxIN_TOL) and Sampling Window
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 5-17 Receiver Input Tolerance (RxIN_TOL) and Sampling Window