JAJSI09I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     DS90UR905Q-Q1 Serializer Pin Functions
    2.     DS90UR906Q-Q1 Deserializer Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Serializer DC Electrical Characteristics
    6. 7.6  Deserializer DC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements for DC and AC Serial Control Bus
    9. 7.9  Timing Requirements for Serializer PCLK
    10. 7.10 Timing Requirements for Serial Control Bus
    11. 7.11 Switching Characteristics: Serializer
    12. 7.12 Switching Characteristics: Deserializer
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
        1. 8.3.3.1 EMI Reduction Features
          1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
        2. 8.3.3.2 Signal Quality Enhancers
          1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 8.3.3.3 Power-Saving Features
          1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
          2. 8.3.3.3.2 Serializer Stop Clock Feature
          3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
        4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 8.3.3.5 Optional Serial Bus Control
        6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
        1. 8.3.4.1  Signal Quality Enhancers
          1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 8.3.4.2  EMI Reduction Features
          1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
          2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
          3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
          4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 8.3.4.3  Power-Saving Features
          1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
          2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
        4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
        5. 8.3.4.5  Deserializer Oscillator Output (Optional)
        6. 8.3.4.6  Deserializer OP_LOW (Optional)
        7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
        8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
        9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
        10. 8.3.4.10 Deserializer Map Select
        11. 8.3.4.11 Deserializer Strap Input Pins
        12. 8.3.4.12 Optional Serial Bus Control
        13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
        1. 8.3.5.1 Sample BIST Sequence
        2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Transmission Media
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Serializer DC Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH High-level input voltage VDDIO = 3.0 to 3.6 V R[7:0],
G[7:0],
B[7:0],
HS, VS, DE,
PCLK, PDB, VODSEL,
RFB,
CONFIG[1:0],BISTEN		 2.2 VDDIO V
VDDIO = 1.71 to 1.89 V 0.65 ×
VDDIO 		VDDIO V
VIL Low-level input voltage VDDIO = 3.0 to 3.6 V GND 0.8 V
VDDIO = 1.71 to 1.89 V GND 0.35 ×
VDDIO 		V
IIN Input current VIN = 0 V or VDDIO VDDIO = 3.0
to 3.6 V		 –15 ±1 +15 μA
VDDIO = 1.7
to 1.89 V		 –15 ±1 +15 μA
LVDS DRIVER DC SPECIFICATIONS
VOD Differential output voltage RL = 100 Ω,
De-emph = disabled, Figure 2 		VODSEL = 0 DOUT+, DOUT– ±205 ±280 ±355 mV
VODSEL = 1 ±320 ±420 ±520
VODp-p Differential output voltage
(DOUT+) – (DOUT-)		 VODSEL = 0 DOUT+, DOUT– 560 mVp-p
VODSEL = 1 840
ΔVOD Output voltage unbalance RL = 100 Ω, De-emph = disabled, VODSEL = L DOUT+, DOUT– 1 50 mV
VOS Offset voltage – single-ended
at TP A and B, Figure 1 		RL = 100 Ω,
De-emph = disabled		 VODSEL = 0 1.65 V
VODSEL = 1 1.575
ΔVOS Offset voltage unbalance
Single-ended
at TP A and B, Figure 1 		RL = 100 Ω, De-emph = disabled DOUT+, DOUT– 1 mV
IOS Output short circuit current DOUT± = 0 V,
De-emph = disabled		 VODSEL = 0 –36 mA
RT Internal termination resistor 80 100 120 Ω
SUPPLY CURRENT
IDDT1 Serializer
supply current
(includes load current)
RL = 100 Ω, f = 65 MHz		 Checker Board Pattern,
De-emph = 3 KΩ
VODSEL = H, Figure 9 		VDD = 1.89 V All VDD pins 75 85 mA
VDDIO = 1.89 V VDDIO 3 5
IDDIOT1 VDDIO = 3.6 V 11 15
IDDT2 Checker Board Pattern,
De-emph = 6 KΩ,
VODSEL = L, Figure 9 		VDD = 1.89 V All VDD pins 65 75 mA
VDDIO = 1.89 V VDDIO 3 5
IDDIOT2 VDDIO = 3.6 V 11 15
IDDZ Serializer
cupply current power down		 PDB = 0 V , (All other LVCMOS Inputs = 0 V) VDD = 1.89 V All VDD pins 40 1000 μA
VDDIO = 1.89 V VDDIO 5 10
IDDIOZ VDDIO = 3.6 V 10 20
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages.