JAJSI09I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     DS90UR905Q-Q1 Serializer Pin Functions
    2.     DS90UR906Q-Q1 Deserializer Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Serializer DC Electrical Characteristics
    6. 7.6  Deserializer DC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements for DC and AC Serial Control Bus
    9. 7.9  Timing Requirements for Serializer PCLK
    10. 7.10 Timing Requirements for Serial Control Bus
    11. 7.11 Switching Characteristics: Serializer
    12. 7.12 Switching Characteristics: Deserializer
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
        1. 8.3.3.1 EMI Reduction Features
          1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
        2. 8.3.3.2 Signal Quality Enhancers
          1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 8.3.3.3 Power-Saving Features
          1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
          2. 8.3.3.3.2 Serializer Stop Clock Feature
          3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
        4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 8.3.3.5 Optional Serial Bus Control
        6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
        1. 8.3.4.1  Signal Quality Enhancers
          1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 8.3.4.2  EMI Reduction Features
          1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
          2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
          3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
          4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 8.3.4.3  Power-Saving Features
          1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
          2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
        4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
        5. 8.3.4.5  Deserializer Oscillator Output (Optional)
        6. 8.3.4.6  Deserializer OP_LOW (Optional)
        7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
        8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
        9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
        10. 8.3.4.10 Deserializer Map Select
        11. 8.3.4.11 Deserializer Strap Input Pins
        12. 8.3.4.12 Optional Serial Bus Control
        13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
        1. 8.3.5.1 Sample BIST Sequence
        2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Transmission Media
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Deserializer DC Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6 V
VIH High-level input voltage PDB, BISTEN 2.2 VDDIO V
VIL Low-level input voltage GND 0.8 V
IIN Input current VIN = 0 V or VDDIO −15 ±1 15 μA
VOH High-level output voltage IOH = −2 mA, OS_PCLK/DATA = L R[7:0], G[7:0], B[7:0], HS,VS, DE, PCLK, LOCK, PASS 2.4 VDDIO V
VOL Low-level output voltage IOL = +2 mA, OS_PCLK/DATA = L R[7:0], G[7:0], B[7:0], HS, VS, DE,PCLK, LOCK, PASS GND 0.4 V
IOS Output short circuit current VDDIO = 3.3 V
VOUT = 0 V, OS_PCLK/DATA = L/H		 PCLK 36 mA
Output short circuit current VDDIO = 3.3 V
VOUT = 0 V, OS_PCLK/DATA = L/H		 Deserializer Outputs 37 mA
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0 V, VOUT = H Outputs −15 15 µA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89 V
VIH High-level input voltage PDB, BISTEN 1.235 VDDIO V
VIL Low-level input voltage GND 0.595 V
IIN Input current VIN = 0 V or VDDIO −15 ±1 15 μA
VOH High-level output voltage IOH = −2 mA, OS_PCLK/DATA = L/H R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS VDDIO − 0.45 VDDIO V
VOL Low-level output voltage IOL = +2 mA, OS_PCLK/DATA = L/H GND 0.45 V
IOS Output short circuit current VDDIO = 1.8 V
VOUT = 0 V, OS_PCLK/DATA = L/H		 PCLK 18 mA
VDDIO = 1.8 V
VOUT = 0 V, OS_PCLK/DATA = L/H		 DATA 18 mA
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO Outputs –15 15 µA
LVDS RECEIVER DC SPECIFICATIONS
VTH Differential input threshold high voltage VCM = +1.2 V (Internal VBIAS) RIN+, RIN- 50 mV
VTL Differential input threshold low voltage –50 mV
VCM Common-mode voltage, internal VBIAS 1.2 V
IIN Input current VIN = 0 V or VDDIO –15 15 µA
RT Internal termination resistor RIN+, RIN- 80 100 120 Ω
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD Differential output voltage RL = 100 Ω CMLOUTP, CMLOUTN 542 mV
VOS Offset voltage
Single-ended		 RL = 100 Ω 1.4 V
RT Internal termination resistor CMLOUTP, CMLOUTN 80 100 120 Ω
SUPPLY CURRENT
IDD1 Deserializer
supply current
(includes load current)		 Checker Board Pattern, OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON
CMLOUTP/N = enabled
CL = 4 pF, Figure 9 		All VDD pins 93 110 mA
IDDIO1 VDDIO 33 45 mA
62 75 mA
IDDZ Deserializer supply current power down PDB = 0 V, All other LVCMOS Inputs = 0 V All VDD pins 40 3000 µA
IDDIOZ VDDIO 5 50 µA
10 100 µA