JAJSI09I
September 2009 – October 2019
DS90UR905Q-Q1
,
DS90UR906Q-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
アプリケーション図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
DS90UR905Q-Q1 Serializer Pin Functions
DS90UR906Q-Q1 Deserializer Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Serializer DC Electrical Characteristics
7.6
Deserializer DC Electrical Characteristics
7.7
DC and AC Serial Control Bus Characteristics
7.8
Timing Requirements for DC and AC Serial Control Bus
7.9
Timing Requirements for Serializer PCLK
7.10
Timing Requirements for Serial Control Bus
7.11
Switching Characteristics: Serializer
7.12
Switching Characteristics: Deserializer
7.13
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
Data Transfer
8.3.2
Video Control Signal Filter — Serializer and Deserializer
8.3.3
Serializer Functional Description
8.3.3.1
EMI Reduction Features
8.3.3.1.1
Serializer Spread Spectrum Compatibility
8.3.3.2
Signal Quality Enhancers
8.3.3.2.1
Serializer VOD Select (VODSEL)
8.3.3.2.2
Serializer De-Emphasis (De-Emph)
8.3.3.3
Power-Saving Features
8.3.3.3.1
Serializer Power-down Feature (PDB)
8.3.3.3.2
Serializer Stop Clock Feature
8.3.3.3.3
1.8-V or 3.3-V VDDIO Operation
8.3.3.4
Serializer Pixel Clock Edge Select (RFB)
8.3.3.5
Optional Serial Bus Control
8.3.3.6
Optional BIST Mode
8.3.4
Deserializer Functional Description
8.3.4.1
Signal Quality Enhancers
8.3.4.1.1
Deserializer Input Equalizer Gain (EQ)
8.3.4.2
EMI Reduction Features
8.3.4.2.1
Deserializer Output Slew (OS_PCLK/DATA)
8.3.4.2.2
Deserializer Common-Mode Filter Pin (CMF) — Optional
8.3.4.2.3
Deserializer SSCG Generation — Optional
8.3.4.2.4
1.8-V or 3.3-V VDDIO Operation
8.3.4.3
Power-Saving Features
8.3.4.3.1
Deserializer Power-Down Feature (PDB)
8.3.4.3.2
Deserializer Stop Stream SLEEP Feature
8.3.4.4
Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
8.3.4.5
Deserializer Oscillator Output (Optional)
8.3.4.6
Deserializer OP_LOW (Optional)
8.3.4.7
Deserializer Pixel Clock Edge Select (RFB)
8.3.4.8
Deserializer Control Signal Filter (Optional)
8.3.4.9
Deserializer Low Frequency Optimization (LF_Mode)
8.3.4.10
Deserializer Map Select
8.3.4.11
Deserializer Strap Input Pins
8.3.4.12
Optional Serial Bus Control
8.3.4.13
Optional BIST Mode
8.3.5
Built-In Self Test (BIST)
8.3.5.1
Sample BIST Sequence
8.3.5.2
BER Calculations
8.3.6
Optional Serial Bus Control
8.4
Device Functional Modes
8.4.1
Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
8.5
Register Maps
9
Application and Implementation
9.1
Application Information
9.1.1
Display Application
9.1.2
Live Link Insertion
9.1.3
Alternate Color / Data Mapping
9.2
Typical Applications
9.2.1
DS90UR905Q-Q1 Typical Connection
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
DS90UR906Q-Q1 Typical Connection
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
10
Power Supply Recommendations
10.1
Power Up Requirements and PDB Pin
11
Layout
11.1
Layout Guidelines
11.1.1
Transmission Media
11.1.2
LVDS Interconnect Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
関連リンク
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHS|48
MPQF159B
サーマルパッド・メカニカル・データ
RHS|48
QFND509A
発注情報
jajsi09i_oa
jajsi09i_pm
8
Detailed Description