JAJSP52C
September 2022 – December 2022
ESD1LIN24-Q1
,
ESD751-Q1
,
ESD761-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings—AEC Specification
6.3
ESD Ratings—IEC Specification
6.4
ESD Ratings - ISO Specification
6.5
Recommended Operating Conditions
6.6
Thermal Information
6.7
Electrical Characteristics
6.8
Typical Characteristics – ESD751
6.9
Typical Characteristics – ESD1LIN24
6.10
Typical Characteristics - ESD761
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
IEC 61000-4-5 Surge Protection
7.3.2
IO Capacitance
7.3.3
Dynamic Resistance
7.3.4
DC Breakdown Voltage
7.3.5
Ultra Low Leakage Current
7.3.6
Clamping Voltage
7.3.7
Industry Standard Packages
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DYF|2
MPSS156
サーマルパッド・メカニカル・データ
発注情報
jajsp52c_oa
jajsp52c_pm
6.9
Typical Characteristics – ESD1LIN24
Figure 6-7
Positive TLP Curve
Figure 6-9
+8-kV Clamped IEC Waveform
Figure 6-11
Capacitance vs. Bias Voltage
Figure 6-8
Negative TLP Curve
Figure 6-10
−8-kV Clamped IEC Waveform
Figure 6-12
DC Voltage Sweep I-V Curve