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DATA SHEET
F28M36x Concerto Microcontrollers
1 Device Overview
1.1 Features
- Master Subsystem — Arm®Cortex®-M3
- 125 MHz
- Embedded memory
- Up to 1MB of flash (ECC)
- Up to 128KB of RAM (ECC or parity)
- Up to 64KB of shared RAM
- 2KB of IPC Message RAM
- Five Universal Asynchronous Receiver/Transmitters (UARTs)
- Four Synchronous Serial Interfaces (SSIs)
and a Serial Peripheral Interface (SPI)
- Two Inter-integrated Circuits (I2Cs)
- Universal Serial Bus On-the-Go (USB-OTG) + PHY
- 10/100 ENET 1588 MII
- Two Controller Area Network, D_CAN, modules (pin-bootable)
- 32-channel Micro Direct Memory Access (µDMA)
- Dual security zones (128-bit password per zone)
- External Peripheral Interface (EPI)
- Micro Cyclic Redundancy Check (µCRC) module
- Four general-purpose timers
- Two watchdog timer modules
- Three external interrupts
- Endianness: little endian
- Clocking
- On-chip crystal oscillator and external clock input
- Dynamic Phase-Locked Loop (PLL) ratio changes supported
- 1.2-V digital, 1.8-V analog, 3.3-V I/O design
- Interprocessor Communications (IPC)
- 32 handshaking channels
- Four channels generate IPC interrupts
- Can be used to coordinate transfer of data through IPC Message RAMs
- Up to 142 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins
- Control Subsystem — TMS320C28x 32-bit CPU
- 150 MHz
- C28x core hardware built-in self-test
- Embedded memory
- Up to 512KB of flash (ECC)
- Up to 36KB of RAM (ECC or parity)
- Up to 64KB of shared RAM
- 2KB of IPC Message RAM
- IEEE-754 single-precision Floating-Point Unit (FPU)
- Viterbi, Complex Math, CRC Unit (VCU)
- Serial Communications Interface (SCI)
- SPI
- I2C
- 6-channel Direct Memory Access (DMA)
- 12 Enhanced Pulse Width Modulator (ePWM) modules
- 24 outputs (16 high-resolution)
- Six 32-bit Enhanced Capture (eCAP) modules
- Three 32-bit Enhanced Quadrature Encoder Pulse (eQEP) modules
- Multichannel Buffered Serial Port (McBSP)
- EPI
- One security zone (128-bit password)
- Three 32-bit timers
- Endianness: little endian
- Analog Subsystem
- Dual 12-bit Analog-to-Digital Converters (ADCs)
- Up to 2.88 MSPS
- Up to 24 channels
- Four Sample-and-Hold (S/H) circuits
- Up to six comparators with 10-bit Digital-to-Analog Converter (DAC)
- Package
- 289-ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
- Temperature options:
- T: –40ºC to 105ºC Junction
- S: –40ºC to 125ºC Junction
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