SPRS825F October   2012  – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. Table 5-2 Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. Table 5-3 Reset (XRS) Timing Requirements
        2. Table 5-4 Reset (XRS) Switching Characteristics
        3. 5.9.1.1   Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. Table 5-5  Input Clock Frequency
          2. Table 5-7  Crystal Oscillator Electrical Characteristics
          3. Table 5-8  X1 Timing Requirements - PLL Enabled
          4. Table 5-9  X1 Timing Requirements - PLL Disabled
          5. Table 5-10 XCLKIN Timing Requirements - PLL Enabled
          6. Table 5-11 XCLKIN Timing Requirements - PLL Disabled
          7. Table 5-12 PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
          1. Table 5-13 Output Clock Frequency
          2. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        4. 5.9.2.4 Internal Clock Frequencies
          1. Table 5-15 Internal Clock Frequencies (150-MHz Devices)
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing – Master Subsystem
        1. Table 5-16 Master Subsystem – Flash/OTP Endurance
        2. Table 5-17 Master Subsystem – Flash Parameters
        3. Table 5-18 Master Subsystem – Flash/OTP Access Timing
        4. Table 5-19 Master Subsystem – Flash Data Retention Duration
      5. 5.9.5 Flash Timing – Control Subsystem
        1. Table 5-21 Control Subsystem – Flash/OTP Endurance
        2. Table 5-22 Control Subsystem – Flash Parameters
        3. Table 5-23 Control Subsystem – Flash/OTP Access Timing
        4. Table 5-24 Control Subsystem – Flash Data Retention Duration
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
          1. Table 5-26 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO - Input Timing
          1. Table 5-27 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
          1. Table 5-28 IDLE Mode Timing Requirements
          2. Table 5-29 IDLE Mode Switching Characteristics
          3. Table 5-30 STANDBY Mode Timing Requirements
          4. Table 5-31 STANDBY Mode Switching Characteristics
          5. Table 5-32 HALT Mode Timing Requirements
          6. Table 5-33 HALT Mode Switching Characteristics
      7. 5.9.7 External Interrupt Electrical Data and Timing
        1. Table 5-34 External Interrupt Timing Requirements
        2. Table 5-35 External Interrupt Switching Characteristics
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
          1. Table 5-36 ADC Electrical Characteristics
          2. Table 5-37 External ADC Start-of-Conversion Switching Characteristics
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. Table 5-38 Electrical Characteristics of the Comparator/DAC
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
          1. Table 5-52 EPI SDRAM Interface Switching Characteristics (see , , and )
          2. Table 5-53 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics (see , , , and )
          3. Table 5-54 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (see and )
          4. Table 5-55 EPI General-Purpose Interface Switching Characteristics (see )
          5. Table 5-56 EPI General-Purpose Interface Timing Requirements (see and )
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
          1. Table 5-57 I2C Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
          1. Table 5-59 Timing Requirements for MIITXCK (see )
          2. Table 5-60 Timing Requirements for MIIRXCK (see )
          3. Table 5-61 Switching Characteristics for EMAC MII Transmit (see )
          4. Table 5-62 Timing Requirements for EMAC MII Receive (see )
        4. 5.11.6.4 MDIO Electrical Data and Timing
          1. Table 5-63 Switching Characteristics for MDIO_CK (see )
          2. Table 5-64 Switching Characteristics for MDIO as Output (see )
          3. Table 5-65 Timing Requirements for MDIO as Input (see )
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
          1. Table 5-66 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. Table 5-67 ePWM Timing Requirements
          2. Table 5-68 ePWM Switching Characteristics
          3. 5.12.1.2.1 Trip-Zone Input Timing
            1. Table 5-69 Trip-Zone Input Timing Requirements
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
          1. Table 5-70 eCAP Timing Requirement
          2. Table 5-71 eCAP Switching Characteristics
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
          1. Table 5-72 eQEP Timing Requirements
          2. Table 5-73 eQEP Switching Characteristics
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
          1. Table 5-74 I2C Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
            1. Table 5-75 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-76 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.12.6.2.2 Slave Mode Timing
            1. Table 5-77 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-78 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
            1. Table 5-79 McBSP Timing Requirements
            2. Table 5-80 McBSP Switching Characteristics
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-81 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-82 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-83 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-84 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-85 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-86 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-87 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-88 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode

The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip select) signals to enable one of four external peripherals; and two BSEL (byte select) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 12 additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without Byte Selects, see Table 5-46 and Table 5-47. For detailed maps of HB-16 Non-Muxed Modes with Byte Selects, see Table 5-48 and Table 5-49.

Table 5-46 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)

EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH
ADDRESS LATCH ENABLE
(CSCFG = 0x0)		 WITH
ONE
CHIP SELECT
(CSCFG = 0x1)		 WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)		 WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0 D0 D0 D0 D0 PH3_GPIO51
EPI0S1 D1 D1 D1 D1 PH2_GPIO50
EPI0S2 D2 D2 D2 D2 PC4_GPIO68
EPI0S3 D3 D3 D3 D3 PC5_GPIO69
EPI0S4 D4 D4 D4 D4 PC6_GPIO70
EPI0S5 D5 D5 D5 D5 PC7_GPIO71
EPI0S6 D6 D6 D6 D6 PH0_GPIO48
EPI0S7 D7 D7 D7 D7 PH1_GPIO49
EPI0S8 D8 D8 D8 D8 PE0_GPIO24
EPI0S9 D9 D9 D9 D9 PE1_GPIO25
EPI0S10 D10 D10 D10 D10 PH4_GPIO52
EPI0S11 D11 D11 D11 D11 PH5_GPIO53
EPI0S12 D12 D12 D12 D12 PF4_GPIO36
EPI0S13 D13 D13 D13 D13 PG0_GPIO40
EPI0S14 D14 D14 D14 D14 PG1_GPIO41
EPI0S15 D15 D15 D15 D15 PF5_GPIO37
 
EPI0S16 A0 A0 A0 A0 PJ0_GPIO56
EPI0S17 A1 A1 A1 A1 PJ1_GPIO57
EPI0S18 A2 A2 A2 A2 PJ2_GPIO58
EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A4 A4 A4 A4 PD2_GPIO18
EPI0S21 A5 A5 A5 A5 PD3_GPIO19
EPI0S22 A6 A6 A6 A6 PB5_GPIO13
EPI0S23 A7 A7 A7 A7 PB4_GPIO12
EPI0S24 A8 A8 A8 A8 PE2_GPIO26
EPI0S25 A9 A9 A9 A9 PE3_GPIO27
EPI0S26 A10 A10 A10 CS0 PH6_GPIO54
EPI0S27 A11 A11 CS1 CS1 PH7_GPIO55
EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62
 
EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60
EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64
 
EPI0S31 x x x x PG7_GPIO47
EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65
EPI0S34 x x x x PE4_GPIO28
EPI0S35 x x x x PE5_GPIO29
EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67
EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66
EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28
EPI0S39 x x x x PG2_GPIO42
EPI0S40 x x x x PG5_GPIO45
EPI0S41 x x x x PG6_GPIO46
EPI0S42 x x x x PN6_GPIO102
EPI0S43 x x x x PN7_GPIO103

Table 5-47 EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)

EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
ACCESSIBLE
BY
Cortex-M3		 ACCESSIBLE
BY
C28x		 WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)		 ACCESSIBLE
BY
Cortex-M3		 ACCESSIBLE
BY
C28x		 WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51
EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50
EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68
EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69
EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70
EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71
EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48
EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49
EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24
EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25
EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52
EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53
EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36
EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40
EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41
EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37
 
EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56
EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57
EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58
EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18
EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19
EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13
EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12
EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26
EPI0S25 A9 PE3_GPIO27 EPI0S25 A9 PE3_GPIO27
EPI0S26 A10 PH6_GPIO54 EPI0S26 A10 PH6_GPIO54
EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67
EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66
EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28
EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42
EPI0S27 A15 PH7_GPIO55 EPI0S40 A15 PG5_GPIO45
EPI0S35 A16 PE5_GPIO29 EPI0S41 A16 PG6_GPIO46
EPI0S40 A17 PG5_GPIO45 EPI0S42 A17 PN6_GPIO102
EPI0S41 A18 PG6_GPIO46 EPI0S43 A18 PN7_GPIO103
EPI0S42 A19 PN6_GPIO102 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62
EPI0S43 A20 PN7_GPIO103 EPI0S27 CS1 PH7_GPIO55
EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28
EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65
EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65    
  EPI0S29 WR PD6_GPIO22 PJ5_GPIO61
EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60
EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64
EPI0S32 RDY PF2_GPIO34 PC0_GPIO64  
  EPI0S31 x PG7_GPIO47
EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29

Table 5-48 EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)

EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
ACCESSIBLE BY Cortex-M3 ACCESSIBLE BY C28x WITH
ADDRESS LATCH ENABLE
(CSCFG = 0x0)		 WITH
ONE
CHIP SELECT
(CSCFG = 0x1)		 WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)		 WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0 D0 D0 D0 D0 PH3_GPIO51
EPI0S1 D1 D1 D1 D1 PH2_GPIO50
EPI0S2 D2 D2 D2 D2 PC4_GPIO68
EPI0S3 D3 D3 D3 D3 PC5_GPIO69
EPI0S4 D4 D4 D4 D4 PC6_GPIO70
EPI0S5 D5 D5 D5 D5 PC7_GPIO71
EPI0S6 D6 D6 D6 D6 PH0_GPIO48
EPI0S7 D7 D7 D7 D7 PH1_GPIO49
EPI0S8 D8 D8 D8 D8 PE0_GPIO24
EPI0S9 D9 D9 D9 D9 PE1_GPIO25
EPI0S10 D10 D10 D10 D10 PH4_GPIO52
EPI0S11 D11 D11 D11 D11 PH5_GPIO53
EPI0S12 D12 D12 D12 D12 PF4_GPIO36
EPI0S13 D13 D13 D13 D13 PG0_GPIO40
EPI0S14 D14 D14 D14 D14 PG1_GPIO41
EPI0S15 D15 D15 D15 D15 PF5_GPIO37
 
EPI0S16 A0 A0 A0 A0 PJ0_GPIO56
EPI0S17 A1 A1 A1 A1 PJ1_GPIO57
EPI0S18 A2 A2 A2 A2 PJ2_GPIO58
EPI0S19 A3 A3 A3 A3 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A4 A4 A4 A4 PD2_GPIO18
EPI0S21 A5 A5 A5 A5 PD3_GPIO19
EPI0S22 A6 A6 A6 A6 PB5_GPIO13
EPI0S23 A7 A7 A7 A7 PB4_GPIO12
EPI0S24 A8 A8 A8 BSEL0 PE2_GPIO26
EPI0S25 A9 A9 BSEL0 BSEL1 PE3_GPIO27
EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54
EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55
EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62
 
EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60
EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64
 
EPI0S31 x x x x PG7_GPIO47
EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65
EPI0S34 x x x x PE4_GPIO28
EPI0S35 x x x x PE5_GPIO29
EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67
EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66
EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28
EPI0S39 x x x x PG2_GPIO42
EPI0S40 x x x x PG5_GPIO45
EPI0S41 x x x x PG6_GPIO46
EPI0S42 x x x x PN6_GPIO102
EPI0S43 x x x x PN7_GPIO103

Table 5-49 EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)

EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
ACCESSIBLE
BY
Cortex-M3		 ACCESSIBLE
BY
C28x		 WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)		 ACCESSIBLE
BY
Cortex-M3		 ACCESSIBLE
BY
C28x		 WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)		 (AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51
EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50
EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68
EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69
EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70
EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71
EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48
EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49
EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24
EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25
EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52
EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53
EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36
EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40
EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41
EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37
 
EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56
EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57
EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58
EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59 EPI0S19 A3 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18
EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19
EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13
EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12
EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26
EPI0S40 A9 PG5_GPIO45 EPI0S40 A9 PG5_GPIO45
EPI0S41 A10 PG6_GPIO46 EPI0S41 A10 PG6_GPIO46
EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67
EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66
EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28
EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42
EPI0S27 A15 PH7_GPIO55 EPI0S42 A15 PN6_GPIO102
EPI0S35 A16 PE5_GPIO29 EPI0S43 A16 PN7_GPIO103
EPI0S42 A17 PN6_GPIO102 EPI0S25 BSEL0 PE3_GPIO27
EPI0S43 A18 PN7_GPIO103 EPI0S26 BSEL1 PH6_GPIO54
EPI0S25 BSEL0 PE3_GPIO27 EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62
EPI0S26 BSEL1 PH6_GPIO54 EPI0S27 CS1 PH7_GPIO55
EPI0S30 CS0 PD7_GPIO23 PJ6_GPIO62 EPI0S34 CS2 PE4_GPIO28
EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65
EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65  
  EPI0S29 WR PD6_GPIO22 PJ5_GPIO61
EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60
EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64
EPI0S32 RDY PF2_GPIO34 PC0_GPIO64  
  EPI0S31 x PG7_GPIO47
EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29