SNOSCY5C August   2014  – October 2024 FDC1004

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Voltage Level
    7. 5.7 I2C Interface Timing
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 The Shield
      2. 6.3.2 The CAPDAC
      3. 6.3.3 Capacitive System Offset Calibration
      4. 6.3.4 Capacitive Gain Calibration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single Ended Measurement
      2. 6.4.2 Differential Measurement
    5. 6.5 Programming
      1. 6.5.1 Serial Bus Address
      2. 6.5.2 Read/Write Operations
      3. 6.5.3 Device Usage
        1. 6.5.3.1 Measurement Configuration
        2. 6.5.3.2 Triggering Measurements
        3. 6.5.3.3 Wait for Measurement Completion
        4. 6.5.3.4 Read of Measurement Result
    6. 6.6 Register Maps
      1. 6.6.1 Registers
        1. 6.6.1.1 Capacitive Measurement Registers
        2. 6.6.1.2 Measurement Configuration Registers
        3. 6.6.1.3 FDC Configuration Register
        4. 6.6.1.4 Offset Calibration Registers
        5. 6.6.1.5 Gain Calibration Registers
        6. 6.6.1.6 Manufacturer ID Register
        7. 6.6.1.7 Device ID Register
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Liquid Level Sensor
      2. 7.1.2 46
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Initialization Set Up
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.2 Read/Write Operations

Access a particular register on the FDC1004 by writing the appropriate value to the Pointer Register. The pointer value is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the FDC1004 requires a value for the pointer register. When reading from the FDC1004, the last value stored in the pointer by a write operation is used to determine which register is read by a read operation. To change the pointer register for a read operation, a new value must be written to the pointer. This transaction is accomplished by issuing the target address byte with the R/W bit low, followed by the pointer byte. No additional data is required. The controller can then generate a START condition and send the target address byte with the R/W bit high to initiate the read command. Note that register bytes are sent MSB first, followed by the LSB. A write operation in a read only registers such as MANUFACTURER ID or SERIAL ID returns a NACK after each data byte; read/write operation to unused address returns a NACK after the pointer; a read/write operation with incorrect I2C address returns a NACK after the I2C address.

FDC1004 Write FrameFigure 6-4 Write Frame
FDC1004 Read FrameFigure 6-5 Read Frame

The I2C interface of the FDC1004 is designed to operate with the standard I2C transactions detailed in the I2C specification; however it is not suitable for use in an I2C system which supports early termination of transactions. A STOP condition or other early termination occurring before the normal end of a transaction (ACK) is not supported and can corrupt that transaction and/or the following transaction.

The device is also sensitive to any extraneous pulse on SDA during the SCL low period of the first bit position of the I2C address byte. To ensure proper operation of the FDC1004, make sure the controller device does not transmit this type of waveform. An example of an unsupported I2C waveform is shown in Figure 6-6.

FDC1004 Extraneous Pulse on SDA between I2C START and ADDRFigure 6-6 Extraneous Pulse on SDA between I2C START and ADDR