SNOSCY5C August 2014 – October 2024 FDC1004
PRODUCTION DATA
These registers configure a digitized capacitance value in the range of -16pF to 16pF (max residual offset 250 aF) that can be added to each channel in order to remove parasitic capacitance due to external circuitry. In addition to the offset calibration capacitance which is a fine-tune offset capacitance, it is possible to support a larger offset by using the CAPDAC (for up to 100pF). These 16-bit registers are formatted as a fixed point number, where the first 5 bits represents the integer portion of the capacitance in Two’s complement format, and the remaining 11 bits represent the fractional portion of the capacitance.
Field Name | Bits | Description | ||
---|---|---|---|---|
OFFSET_CALn(1) | [15:11] | Integer part | Integer portion of the Offset Calibration of Channel CINn | |
[10:0] | Decimal part | Decimal portion of the Offset Calibration of Channel CINn |