JAJSC67A May 2016 – October 2024 FDC2112-Q1 , FDC2114-Q1 , FDC2212-Q1 , FDC2214-Q1
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tSDWAKEUP | Wake-up time from SD high-low transition to I2C readback | 2 | ms | ||
tSLEEPWAKEUP | Wake-up time from sleep mode | 0.05 | ms | ||
tWD-TIMEOUT | Sensor recovery time (after watchdog timeout) | 5.2 | ms | ||
I2C TIMING CHARACTERISTICS | |||||
fSCL | Clock frequency | 10 | 400 | kHz | |
tLOW | Clock low time | 1.3 | μs | ||
tHIGH | Clock high time | 0.6 | μs | ||
tHD;STA | Hold time (repeated) START condition: after this period, the first clock pulse is generated | 0.6 | μs | ||
tSU;STA | Setup time for a repeated START condition | 0.6 | μs | ||
tHD;DAT | Data hold time | 0 | μs | ||
tSU;DAT | Data setup time | 100 | ns | ||
tSU;STO | Setup time for STOP condition | 0.6 | μs | ||
tBUF | Bus free time between a STOP and START condition | 1.3 | μs | ||
tVD;DAT | Data valid time | 0.9 | μs | ||
tVD;ACK | Data valid acknowledge time | 0.9 | μs | ||
tSP | Pulse width of spikes that must be suppressed by the input filter(1) | 50 | ns |