The FPC202 can be configured to pre-fetch data from each downstream port’s module. The pre-fetched data is stored locally in the FPC202's memory, allowing any downstream read operations in the pre-fetch range to be directly read from the FPC202 rather than waiting for the FPC202 to read from the downstream device through I2C. The FPC202 can pre-fetch data from the ports on a one-time basis, a regular basis (periodic pre-fetch), or upon the occurrence of certain events (interrupt-driven pre-fetch).

For periodic pre-fetching, the period is configured in steps of 5 ms from 0 to 1.275 s, where 0 is a one-time pre-fetch. The pre-fetched range is determined by two settings, the pre-fetch length and the pre-fetch offset address. The FPC202 will pre-fetch beginning at the offset address for a length of bytes between 1 and 32. The target device address is set to either 0xA0 or 0xA2. Once configured, the start bit is set to begin periodic pre-fetching and the stop bit is set to stop pre-fetching. After a pre-fetch is completed, the gate bit is set to '0', and any attempted read operation in the pre-fetched range will return data from the FPC202's memory containing the last pre-fetched data. To modify the pre-fetched range or to stop the FPC202 from returning the data from memory, the gate bit must be reset to '1'. If the FPC202 receives a NACK during a pre-fetch attempt, the gate bit will automatically be reset. Each port has its own gate bit and separate memory and settings.

For interrupt-driven pre-fetch, the interrupt event can be configured for either the rising- or falling-edge of one of the IN_[A,B,C] input signals of a port. The pre-fetch range and target device address is configured similarly but independently of the periodic pre-fetch settings. Interrupt-driven pre-fetch also has a gate bit and memory independent of the periodic pre-fetch. Once an interrupt-driven pre-fetch occurs successfully, an interrupt is triggered on the HOST_INT_N pin and the aggregated interrupt flag for that port will be set. For the interrupt to be cleared and for another interrupt pre-fetch to occur, it must be re-armed with a register write. If the pre-fetch attempt is NACK'd, the gate bit will not be set, the interrupt will not be generated, and the interrupt-driven pre-fetch does not need to be re-armed. Note that the pre-fetched data from the interrupt-driven pre-fetch has precedence over the data from a periodic pre-fetch if they have overlapping pre-fetch ranges. The FPC202 will return data from the interrupt-driven pre-fetch even if the periodic pre-fetch data is more recent. When an interrupt-driven pre-fetch occurs, it is recommended that it is dealt with immediately by reading the pre-fetched data and re-arming it.

Request access to the FPC202 Programmer's Guide (SNLU229) here for more details on how to configure data pre-fetch.