JAJSSV1B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

MINNOMMAXUNIT
GENERAL TIMING REQUIREMENTS
TPORInternal power-on reset (PoR) timeTime between stable VDD1 power supply (VDD1 ≥ 3.3V - 5%) and de-assertion of internal PoR. The port-side and host-side control interfaces (I2C and/or SPI) are not operational during this time.3050ms
HOST-SIDE SPI TIMING REQUIREMENTS (PROTOCOL_SEL =GND) (1)(2)
fSPI0.110MHz
tHI-SCK0.4 ÷ fSPIns
tLO-SCK0.4 ÷ fSPIns
tHD-MOSI1ns
tSU-MOSI1ns
tHD-SSN4ns
tSU-SSN1.2ns
tOFF-SSNFor writes and local FPC202 register reads1μs
For consecutive downstream (remote) register reads on the same port, assuming 400 KHz I2C170
For consecutive downstream (remote) register reads on the same port, assuming 100 KHz I2C620
tODZ-MISOMISO (CTRL4) driven-to-TRI_STATE time32ns
tOZD-MISOMISO (CTRL4) TRI_STATE-to-driven time10ns
tODMISO (CTRL4) output delay time15ns
HOST-SIDE I2C TIMING REQUIREMENTS (PROTOCOL_SEL=FLOAT OR HIGH)(2)(3)(4)
fSCLHost-side I2C clock frequency (CTRL1) in I2C mode1001000kHz
tBUFBus free time between STOP and START condition0.5μs
tHD-STAHold time after (repeated) START condition. After this period, the first clock is generated.After this period, the first clock can be generated by the master.0.3μs
tSU-STARepeated START condition setup time0.3μs
tSU-STOSTOP condition setup time0.3μs
tHD-DATSDA (CTRL2) hold time32ns
tSU-DATSDA (CTRL2) setup timeApplies to standard-mode I2C, 100 kHz250ns
SDA (CTRL2) setup timeApplies to fast-mode I2C, 400 kHz100ns
SDA (CTRL2) setup timeApplies to fast-mode plus I2C, 1000 kHz50ns
tLOWSCL (CTRL1) clock low time0.5μs
tHIGHSCL (CTRL1) clock high time0.3μs
tRSDA (CTRL2) rise time, readApplies to standard-mode I2C, 100 kHz1000ns
SDA (CTRL2) rise time, readApplies to fast-mode I2C, 400 kHz20300ns
SDA (CTRL2) rise time, readApplies to fast-mode plus I2C, 1000 kHz120ns
tFSDA (CTRL2) fall time, readApplies to standard-mode I2C, 100 kHz300ns
SDA (CTRL2) fall time, readApplies to fast-mode I2C, 400 kHz4.4300ns
SDA (CTRL2) fall time, readApplies to fast-mode plus I2C, 1000 kHz4.4120ns
(1) SPI operation is available TPOR milliseconds after VDD1 power up, provided EN = high or float and VDD2 is stable.
(2) These parameters are not production tested.
(3) I2C operation is available TPOR milliseconds after VDD1 power up, provided EN = high or float and VDD2 is stable.
(4) These specifications support I2C Rev 6 specifications