JAJSSV1B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.1 Design Requirements

For this design example, the following guidelines outlined in Table 8-1 apply.

Table 8-1 SFP/QSFP Application Design Guidelines
DESIGN PARAMETER REQUIREMENT
FPC202 physical placement

The FPC202 package is small enough to fit underneath an SFP or QSFP cage, on the opposite side of the board.

For SFP applications, such a placement leaves 4.6 mm of air gap between the FPC202 package edge and the SFP pressfit pins (assuming 14.25 mm pin-to-pin spacing for a stacked SFP cage).

For QSFP applications, such a placement leaves 7.2 mm of air gap between the FPC202 package edge and the QSFP pressfit pins (assuming 19.5 mm pin-to-pin spacing for a stacked QSFP cage).
LED implementation The FPC202 is designed to drive active-low LEDs which have their anode connected to the port-side 3.3-V supply. Refer to Section 7.3.2.
Port-side I2C SDA and SCL pull-ups As per the SFF-8431 and SFF-8436 specification, the port-side (downstream) SCL and SDA nets should be pulled up to 3.3 V using resistors in the 4.7-kΩ to 10-kΩ range.
QSFP ModSelL QSFP provides a mechanism to enable or disable the port’s I2C interface. Since the FPC202 has a separate I2C master to communicate with each port, the ModSelL input for every QSFP can be connected to GND, thereby permanently enabling each QSFP port’s I2C bus.
SFP/QSFP port power supply de-coupling Follow the SFF-8431 and SFF-8436 recommendations for power supply de-coupling.