JAJSLL4C December   2016  – January 2021 HD3SS213

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HD3SS213 AUX Channel in 2:1 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 HD3SS213 AUX Channel in 1:2 Application
        1.       Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Differential Traces
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3 Recommended Operating Conditions

Typical values for all parameters are at VCC = 3.3 V and TA = 25°C (unless otherwise noted). All temperature limits are specified by design.
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
VDDSupply voltage33.33.6V
VIHInput high voltageControl pins and signal pins (Dx_SEL, AUX_SEL, OE, HPDx)2VDDV
VIMInput mid level voltageAUX_SEL pinVDD/2
– 300 mV		VDD/2VDD/2
+ 300 mV		V
VILInput low voltageControl pins and signal pins (Dx_SEL, AUX_SEL, OE, HPDx)–0.10.8V
VI/O_DiffDifferential voltage
(Dx, AUXx)		Switch I/O differential voltage01.8VPP
VI/O_CMDx switching I/O common-mode voltageSwitch I/O common-mode voltage02V
AUXx switching I/O common-mode voltageSwitch I/O common-mode voltage03.6V
IIHInput high current
(Dx_SEL, AUX_SEL)		VDD = 3.6 V, VIN = VDD1µA
IIMInput mid level current
(AUX_SEL)		VDD = 3.6V, VIN = VDD/21µA
IILInput low current
(Dx_SEL, AUX_SEL)		VDD = 3.6 V, VIN = GND1µA
ILKLeakage current
(Dx_SEL, AUX_SEL)		VDD = 3.3 V, VI = 2 V, OE = 3.3 V1µA
Leakage current (HPDx)VDD = 3.3 V, VI = 2 V, OE = 3.3 V, Dx_SEL = 3.3 V1µA
VDD = 3.3 V, VI = 2 V, OE = 3.3 V, Dx_SEL = GND1
IoffDevice shut down currentVDD = 3.6 V, OE = GND2.5µA
IDDSupply currentVDD = 3.6 V,
Dx_SEL or AUX_SEL = VDD or GND		0.61mA
DA, DB, DC HIGH SPEED SIGNAL PATH
CONOutputs ON capacitanceVI = 0 V, outputs open, switch ON1.5pF
COFFOutputs OFF capacitanceVI = 0 V, outputs open, switch OFF1pF
RONON resistanceVDD = 3.3 V, VCM = 0.5 V to 1.5 V,
IO = –40 mA		812Ω
ΔRONON resistance match between pairs of the same channelVDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2V,
IO = –40 mA		1.5Ω
RFLAT_ONON resistance flatness,
RON(max) – RON(min)		VDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2 V1.3Ω
AUXx, DDC SIGNAL PATH
CONOutputs ON capacitanceVI = 0 V, outputs open, switch ON9pF
COFFOutputs OFF capacitanceVI = 0 V, outputs open, switch OFF3pF
RON(AUX)ON resistanceVDD = 3.3 V, VCM = 0 V – VDD, IO = –8 mA610Ω
RON(DDC)ON resistance on DDC channelVDD = 3.3 V, VCM = 0.4 V, IO = –3 mA2030Ω