JAJSQA1C december   2015  – december 2020 HD3SS214

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-AEF84F8B-5035-497D-BF42-BEE5DCF32E24/SLAS9018663 #GUID-AEF84F8B-5035-497D-BF42-BEE5DCF32E24/SLAS9012713
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics, Device Parameters
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Speed Switching
      2. 7.3.2 HPD, AUX, and DDC Switching
      3. 7.3.3 Output Enable and Power Savings
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Dual GPU With Docking Station Support
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 DP Inputs
        2. 8.2.3.2 Source Selection Interface
      4. 8.2.4 DP++ Support
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1 AUX and DDC Switching
          2. 8.2.4.2.2 CONFIG1 and CONFIG2 Routing
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Differential Traces
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Device Functional Modes

The HD3SS214 behaves as a two to one or one to two using high bandwidth pass gates. The input ports are selected using the Dx_SEL pin and Dx_SEL pin which are shown in Table 7-1.

Table 7-1 AUX/DDC Switch Control Logic(2)
CONTROL LINESSWITCHED I/O PINS(1)
AUX_SELDx_SELDCz(p) Pin
z = 0, 1 ,2 or 3		DCz(n) Pin
z = 0, 1 ,2 or 3		HPDC PinAUXAAUXBAUXCDDCADDCBDDCC
LLDAz(p)DAz(n)HPDATo/From AUXCZTo/From AUXAZZZ
LHDBz(p)DBz(n)HPDBZTo/From AUXCTo/From AUXBZZZ
HLDAz(p)DAz(n)HPDAZZTo/From DDCATo/From AUXCZZ
HHDBz(p)DBz(n)HPDBZZTo/From DDCBZTo/From AUXCZ
M(1)LDAz(p)DAz(n)HPDATo/From AUXCZTo/From AUXATo/From DDCCZTo/From DDCA
M(1)HDBz(p)DBz(p)HPDBZTo/From AUXCTo/From AUXBZTo/From DDCCTo/From DDCB
(1) Z = High Impedance
(2) OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch. Note: The ports which are not selected by the control lines will be in high impedance status.