JAJSJQ2C june 2021 – march 2023 HDC3020-Q1 , HDC3021-Q1 , HDC3022-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Parameter | FAST MODE | FAST MODE PLUS | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
f(SCL) | SCL operating frequency | 1 | 400 | 1 | 1000 | kHz | |
t(BUF) | Bus-free time between STOP and START conditions | 1.3 | 0.5 | µs | |||
t(SUSTA) | Repeated START condition setup time | 0.6 | 0.26 | µs | |||
t(HDSTA) | Hold time after repeated START condition. After this period, the first clock is generated. |
0.6 | 0.26 | µs | |||
t(SUSTO) | STOP condition setup time | 0.6 | 0.26 | µs | |||
t(HDDAT) | Data hold time(2) | 0 | 900 | 0 | 150 | ns | |
t(SUDAT) | Data setup time | 100 | 50 | ns | |||
t(LOW) | SCL clock low period | 1.3 | 0.5 | µs | |||
t(HIGH) | SCL clock high period | 0.6 | 0.26 | µs | |||
t(VDAT) | Data valid time (data response time)(3) | 0.9 | 0.45 | µs | |||
tR | SDA, SCL rise time | 20 | 300 | 120 | ns | ||
tF | SDA, SCL fall time | 20 x (VDD / 5.5 V) |
300 | 20 x (VDD / 5.5 V) |
120 | ns | |
tLPF | Glitch suppression filter | 50 | 50 | ns |