JAJSCM7E June   2009  – January 2016 INA220

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Bus Timing Diagram Definitions
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
        1. 8.3.1.1 Power Measurement
        2. 8.3.1.2 PGA Function
        3. 8.3.1.3 Compatibility With TI Hot Swap Controllers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the INA220 Calibration Register
      2. 8.5.2 Programming the INA220 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Bus Overview
        1. 8.5.4.1 Serial Bus Address
        2. 8.5.4.2 Serial Interface
      5. 8.5.5 Writing to and Reading from the INA220
        1. 8.5.5.1 High-Speed Two-Wire Mode
        2. 8.5.5.2 Power-Up Conditions
    6. 8.6 Register Maps
      1. 8.6.1 Register Information
      2. 8.6.2 Register Details
        1. 8.6.2.1 Configuration Register (address = 00h) [reset = 399Fh]
      3. 8.6.3 Data Output Registers
        1. 8.6.3.1 Shunt Voltage Register (address = 01h)
        2. 8.6.3.2 Bus Voltage Register (address = 02h)
        3. 8.6.3.3 Power Register (address = 03h) [reset = 00h]
        4. 8.6.3.4 Current Register (address = 04h) [reset =00h]
      4. 8.6.4 Calibration Register
        1. 8.6.4.1 Calibration Register (address = 05h) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Register Results for the Example Circuit
      3. 9.2.3 Typical Application: -48-V Telecom Current/Voltage/Power Sense With Isolation
      4. 9.2.4 Typical Application: 48-V Telecom Current/Voltage/Power Sense
      5. 9.2.5 Typical Application: General Source Low-Side Sensing
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
VS Supply voltage 6 V
Analog inputs
IN+, IN–		 Differential (VIN+) – (VIN–)(2) –26 26 V
Common-mode (VIN+ + VIN-) / 2 –0.3 26 V
VVBUS Voltage at VBUS pin –0.3 26 V
VSDA Voltage at SDA pin GND – 0.3 6 V
VSCL Voltage at SCL pin GND – 0.3 VS + 0.3 V
Input current into any pin 5 mA
Open-drain digital output current 10 mA
Operating temperature –40 125 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IN+ and IN– may have a differential voltage of –26 to 26 V; however, the voltage at these pins must not exceed the range of –0.3 to 26 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Machine model (MM) ±150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCM (VIN+ + VIN-) / 2 12 V
VS Supply voltage 3.3 V
TA Ambient temperature –40 85 ºC

7.4 Thermal Information

THERMAL METRIC(1) INA220 UNIT
DGS (VSSOP)
10 PINS
RθJA Junction-to-ambient thermal resistance 165.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.2 °C/W
RθJB Junction-to-board thermal resistance 86.6 °C/W
ψJT Junction-to-top characterization parameter 6.4 °C/W
ψJB Junction-to-board characterization parameter 85.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, VVBUS = 12 V, PGA = /1, and BRNG(1) = 1, unless otherwise noted.
TEST CONDITIONS INA220A INA220B UNIT
MIN TYP MAX MIN TYP MAX
INPUT
Full-scale current sense (input) voltage range VSHUNT PGA = /1 0 ±40 0 ±40 mV
PGA = /2 0 ±80 0 ±80 mV
PGA = /4 0 ±160 0 ±160 mV
PGA = /8 0 ±320 0 ±320 mV
Bus voltage (input voltage)(3) BRNG = 1 0 32 0 32 V
BRNG = 0 0 16 0 16 V
Common-mode rejection VIN+ = 0 to 26 V 100 120 100 120 dB
Offset Voltage, RTI(4) VOS PGA = /1 ±10 ±100 ±10 ±50(2) μV
PGA = /2 ±20 ±125 ±20 ±75(2) μV
PGA = /4 ±30 ±150 ±30 ±75(2) μV
PGA = /8 ±40 ±200 ±40 ±100(2) μV
TA = –40°C to 85°C 0.16 0.16 μV/°C
versus power supply PSRR VS = 3 to 5.5 V 10 10 μV/V
Current sense gain error ±40 ±40 m%
TA = –40°C to 85°C 1 1 m%/°C
IN+ pin input impedance Active mode 20 20 μA
IN– pin input impedance Active mode 20 20 μA
VBUS pin input impedance(6) Active mode 320 320 kΩ
IN+ pin input leakage(5) Power-down mode 0.1 ±0.5 0.1 ±0.5 μA
IN– pin input leakage(5) Power-down mode 0.1 ±0.5 0.1 ±0.5 μA
DC ACCURACY
ADC basic resolution 12 12 bits
Shunt voltage 1-LSB step size 10 10 μV
Bus voltage 1-LSB step size 4 4 mV
Current measurement error ±0.2% ±0.5% ±0.2% ±0.3%(2)
over Temperature
TA = –40°C to 85°C		 ±1% ±0.5%(2)
Bus voltage measurement error VBUS = 12 V ±0.2% ±0.5% ±0.2% ±0.5%
over Temperature
TA = –40°C to 85°C		 ±1% ±1%
Differential nonlinearity ±0.1 ±0.1 LSB
ADC TIMING
ADC conversion time 12-bit 532 586 532 586 μs
11-bit 276 304 276 304 μs
10-bit 148 163 148 163 μs
9-bit 84 93 84 93 μs
Minimum convert input low time 4 4 μs
SMBus
SMBus timeout(7) 28 35 28 35 ms
DIGITAL INPUTS (SDA as Input, SCL, A0, A1)
Input capacitance 3 3 pF
Leakage input current 0 ≤ VIN ≤ VS 0.1 1 0.1 1 μA
VIH input logic level 0.7 (VS) 6 0.7 (VS) 6 V
VIL input logic level –0.3 0.3 (VS) –0.3 0.3 (VS) V
Hysteresis 500 500 mV
OPEN-DRAIN DIGITAL OUTPUTS (SDA)
Logic 0 output level ISINK = 3 mA 0.15 0.4 0.15 0.4 V
High-level output leakage current VOUT = VS 0.1 1 0.1 1 μA
POWER SUPPLY
Operating supply range 3 5.5 3 5.5 V
Quiescent current 0.7 1 0.7 1 mA
Quiescent current, power-down mode 6 15 6 15 μA
Power-on reset threshold 2 2 V
(1) BRNG is bit 13 of the Configuration Register 00h (see Figure 19).
(2) Indicates improved specifications of the INA220B.
(3) This parameter only expresses the full-scale range of the ADC scaling. In no event should more than 26 V be applied to this device.
(4) Referred-to-input (RTI)
(5) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of the table. Negative leakage currents can occur under different input conditions.
(6) The input impedance of this pin may vary approximately ±15%.
(7) SMBus timeout in the INA220 resets the interface any time SCL or SDA is low for more than 28 ms.

7.6 Bus Timing Diagram Definitions(1)

FAST MODE HIGH-SPEED MODE UNIT
MIN TYP MAX MIN TYP MAX
ƒ(SCL) SCL operating frequency 0.001 0.4 0.001 2.56 MHz
t(BUF) Bus free time between STOP and START condition 1300 160 ns
t(HDSTA) Hold time after repeated START condition
After this period, the first clock is generated.		 600 160 ns
t(SUSTA) Repeated START condition setup time 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
t(HDDAT) Data hold time 0 900 0 90 ns
t(SUDAT) Data setup time 100 10 ns
t(LOW) SCL clock LOW period 1300 250 ns
t(HIGH) SCL clock HIGH period 600 60 ns
tFDA Data fall time 300 150 ns
tFCL Clock fall time 300 40 ns
tRCL Clock rise time 300 40 ns
tRCL Clock rise time for SCLK ≤ 100 kHz 1000 ns
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not production tested. Condition: A0=A1=0.
INA220 ai_tim_bus_bos459.gif Figure 1. Bus Timing Diagram

7.7 Typical Characteristics

at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, PGA = /1, and BRNG = 1, unless otherwise noted.
INA220 tc_frq_resp_bos459.gif
Figure 2. Frequency Response
INA220 tc_shunt_g-tmp_bos459.gif
Figure 4. ADC Shunt Gain Error vs Temperature
INA220 tc_bus_g-tmp_bos459.gif
Figure 6. ADC Bus Gain Error vs Temperature
INA220 tc_in_curr_v_bos459.gif
Figure 8. Input Currents With Large Differential Voltages (VIN+ at 12 V, Sweep Of VIN–)
INA220 tc_shutdwn-tmp_bos459.gif
Figure 10. Shutdown IQ vs Temperature
INA220 tc_total_bus_error_v_vsup_bos459.gif
Figure 12. Total Percent Bus Voltage Error
vs Supply Voltage
INA220 tc_shunt_off-tmp_bos459.gif
Figure 3. ADC Shunt Offset vs Temperature
INA220 tc_bus_off-tmp_bos459.gif
Figure 5. ADC Bus Voltage Offset vs Temperature
INA220 tc_inl-vin_bos459.gif
Figure 7. Integral Nonlinearity vs Input Voltage
INA220 tc_iq-tmp_bos459.gif
Figure 9. Active IQ vs Temperature
INA220 tc_iq-i2c_bos459.gif
Figure 11. Active IQ vs Two-Wire Clock Frequency
INA220 tc_shutdwn-frq_bos459.gif
Figure 13. Shutdown IQ vs Two-Wire Clock Frequency