JAJSCM7E June   2009  – January 2016 INA220

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Bus Timing Diagram Definitions
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
        1. 8.3.1.1 Power Measurement
        2. 8.3.1.2 PGA Function
        3. 8.3.1.3 Compatibility With TI Hot Swap Controllers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the INA220 Calibration Register
      2. 8.5.2 Programming the INA220 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Bus Overview
        1. 8.5.4.1 Serial Bus Address
        2. 8.5.4.2 Serial Interface
      5. 8.5.5 Writing to and Reading from the INA220
        1. 8.5.5.1 High-Speed Two-Wire Mode
        2. 8.5.5.2 Power-Up Conditions
    6. 8.6 Register Maps
      1. 8.6.1 Register Information
      2. 8.6.2 Register Details
        1. 8.6.2.1 Configuration Register (address = 00h) [reset = 399Fh]
      3. 8.6.3 Data Output Registers
        1. 8.6.3.1 Shunt Voltage Register (address = 01h)
        2. 8.6.3.2 Bus Voltage Register (address = 02h)
        3. 8.6.3.3 Power Register (address = 03h) [reset = 00h]
        4. 8.6.3.4 Current Register (address = 04h) [reset =00h]
      4. 8.6.4 Calibration Register
        1. 8.6.4.1 Calibration Register (address = 05h) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Register Results for the Example Circuit
      3. 9.2.3 Typical Application: -48-V Telecom Current/Voltage/Power Sense With Isolation
      4. 9.2.4 Typical Application: 48-V Telecom Current/Voltage/Power Sense
      5. 9.2.5 Typical Application: General Source Low-Side Sensing
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The INA220 is a digital current sense amplifier with an I2C- and SMBus-compatible interface. It provides digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution as well as continuous-versus-triggered operation. Detailed register information appears at the end of this data sheet, beginning with Table 2. See Functional Block Diagram for a block diagram of the INA220 device.

8.2 Functional Block Diagram

INA220 ai_reg_fbd_bos448.gif

8.3 Feature Description

8.3.1 Basic ADC Functions

The two analog inputs to the INA220, IN+ and IN–, connect to a shunt resistor in the bus of interest. Bus voltage is measured at VBUS pin. The INA220 is typically powered by a separate supply from 3 to 5.5 V. The bus being sensed can vary from 0 to 26 V. It requires no special considerations for power-supply sequencing (for example, a bus voltage can be present with the supply voltage off, and vice-versa). The INA220 senses the small drop across the shunt for shunt voltage, and senses the voltage with respect to ground from VBUS pin for the bus voltage.

When the INA220 is in the normal operating mode (that is, MODE bits of the Configuration register are set to 111), it continuously converts the shunt voltage up to the number set in the shunt voltage averaging function (Configuration register, SADC bits). The device then converts the bus voltage up to the number set in the bus voltage averaging (Configuration register, BADC bits). The Mode control in the Configuration register also permits selecting modes to convert only voltage or current, either continuously or in response to an event (triggered).

All current and power calculations are performed in the background and do not contribute to conversion time; conversion times shown in Electrical Characteristics can be used to determine the actual conversion time.

Power-down mode reduces the quiescent current and turns off current into the INA220 inputs, avoiding any supply drain. Full recovery from power-down requires 40 μs. ADC off mode (set by the Configuration register, MODE bits) stops all conversions.

In triggered mode, writing any of the triggered convert modes into the Configuration register (even if the desired mode is already programmed into the register) triggers a single-shot conversion.

Although the INA220 can be read at any time, and the data from the last conversion remain available, the Conversion Ready bit (Status register, CNVR bit) is provided to help coordinate one-shot or triggered conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are complete.

The Conversion Ready bit clears under any of these conditions:

  • Writing to the Configuration register, except when configuring the MODE bits for power down or ADC off (disable) modes
  • Reading the Status register
  • Triggering a single-shot conversion with the convert pin

8.3.1.1 Power Measurement

Current and bus voltage are converted at different points in time, depending on the resolution and averaging mode settings. For instance, when configured for 12-bit and 128-sample averaging, up to 68 ms in time between sampling these two values is possible. Again, these calculations are performed in the background and do not add to the overall conversion time.

8.3.1.2 PGA Function

If larger full-scale shunt voltages are desired, the INA220 provides a PGA function that increases the full-scale range up to 2, 4, or 8 times (320 mV). Additionally, the bus voltage measurement has two full-scale ranges: 16 or 32 V.

8.3.1.3 Compatibility With TI Hot Swap Controllers

The INA220 is designed for compatibility with hot swap controllers such the TI TPS2490. The TPS2490 uses a high-side shunt with a limit at 50 mV; the INA220 full-scale range of 40 mV enables the use of the same shunt for current sensing below this limit. When sensing is required at (or through) the 50-mV sense point of the TPS2490, the PGA of the INA220 can be set to /2 to provide an 80-mV full-scale range.

8.4 Device Functional Modes

8.4.1 Filtering and Input Considerations

Measuring current is often noisy, and such noise can be difficult to define. The INA220 offers several options for filtering by choosing resolution and averaging in the Configuration register. These filtering options can be set independently for either voltage or current measurement.

The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be dealt with by incorporating filtering at the input of the INA220. The high frequency enables the use of low-value series resistors on the filter for negligible effects on measurement accuracy. In general, filtering the INA220 input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (>1 MHz). Filter using the lowest possible series resistance and ceramic capacitor. TI recommends values of 0.1 to 1 μF. Figure 14 shows the INA220 with an additional filter added at the input.

Overload conditions are another consideration for the INA220 inputs. The INA220 inputs are specified to tolerate 26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long the power supply or energy storage capacitors support it). It must be remembered that removing a short to ground can result in inductive kickbacks that could exceed the 26-V differential and common-mode rating of the INA220. Inductive kickback voltages are best dealt with by Zener-type transient-absorbing devices combined with sufficient energy storage capacitance.

In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem occurs because an excessive dV/dt can activate the ESD protection in the INA220 in systems where large currents are available. Testing has demonstrated that the addition of 10-Ω resistors in series with each input of the INA220 sufficiently protects the inputs against dV/dt failure up to the 26-V rating of the INA220. These resistors have no significant effect on accuracy.

INA220 ai_input_filtering_bos459.gif Figure 14. INA220 With Input Filtering

8.5 Programming

8.5.1 Programming the INA220 Calibration Register

Register Details shows the default power-up states of the registers. These registers are volatile, and if programmed to anything other than default values, they must be reprogrammed at every device power-up. The Calibration Register is calculated based on Equation 1. This equation includes the term Current_LSB, which is the programmed value for the LSB for the Current Register (04h). The Current_LSB value is used to convert the value in the Current Register (04h) to the actual current in amperes. The highest resolution for the Current Register (04h) can be obtained by using the smallest allowable Current_LSB based on the maximum expected current as shown in Equation 2. While this value yields the highest resolution, it is common to select a value for the Current_LSB to the nearest round number above this value to simplify the conversion of the Current Register (04h) and Power Register (03h) to amperes and watts respectively. The RSHUNT term is the value of the external shunt used to develop the differential voltage across the input pins. The Power Register (03h) is internally set to be 20 times the programmed Current_LSB (see Equation 3).

Equation 1. INA220 q_cal_value_04_bas459.gif

where

  • 0.04096 is an internal fixed value used to ensure scaling is maintained properly
  • Current_LSB is the programmed value for the LSB for the Current Register (04h)
Equation 2. INA220 q_currlsb_Maximum_bos459.gif
Equation 3. INA220 q_powerlsb_05_bas459.gif

Shunt voltage is calculated by multiplying the Shunt Voltage Register contents with the Shunt Voltage LSB of 10 μV. The Bus Voltage register bits are not right-aligned. To compute the value of the Bus Voltage, Bus Voltage Register contents must be shifted right by three bits. This shift puts the BD0 bit in the LSB position so that the contents can be multiplied by the Bus Voltage LSB of 4-mV to compute the bus voltage measured by the device. After programming the Calibration Register, the value expected in the Current Register (04h) can be calculated by multiplying the Shunt Voltage register contents by the Calibration Register and then dividing by 4096 as shown in Equation 4. To obtain a value in amperes, the Current register value is multiplied by the programmed Current_LSB.

Equation 4. INA220 q_current_bas459.gif

The value expected in the Power register (03h) can be calculated by multiplying the Current register value by the Bus Voltage register value and then dividing by 5000 as shown in Equation 5. Power Register content is multiplied by Power LSB which is 20 times the Current_LSB for a power value in watts.

Equation 5. INA220 q_power_bos448.gif

8.5.2 Programming the INA220 Power Measurement Engine

8.5.2.1 Calibration Register and Scaling

The Calibration register makes it possible to set the scaling of the Current and Power registers to whatever values are most useful for a given application. One strategy may be to set the Calibration register such that the largest possible number is generated in the Current register or Power register at the expected full-scale point; this approach yields the highest resolution. The Calibration register can also be selected to provide values in the Current and Power registers that either provide direct decimal equivalents of the values being measured, or yield a round LSB number. After these choices have been made, the Calibration register also offers possibilities for end-user system-level calibration, where the value is adjusted slightly to cancel total system error. After determining the exact current by using an external ammeter, the value of the Calibration Register can then be adjusted based on the measured current result of the INA220 to cancel the total system error as shown in Equation 6.

Equation 6. INA220 q_currlsb_09_bos448.gif

8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)

The INA220 can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default 12-bit resolution, 320-mV shunt full-scale range (PGA = /8), 32-V bus full-scale range, and continuous conversion of shunt and bus voltage.

Without programming, current is measured by reading the shunt voltage. The Current register and Power register are only available if the Calibration register contains a programmed value.

8.5.4 Bus Overview

The INA220 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another.

The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is being addressed. Two lines, SCL and SDA, connect the INA220 to the bus. Both SCL and SDA are open-drain connections.

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions.

To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a START or STOP condition.

After all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from low to high while SCL is high. The INA220 includes a 28-ms timeout on its interface to prevent locking up an SMBus.

8.5.4.1 Serial Bus Address

To communicate with the INA220, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation.

The INA220 has two address pins, A0 and A1. Table 1 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any activity on the interface occurs. The address pins are read at the start of each communication event.

Table 1. INA220 Address Pins and Slave Addresses

A1 A0 SLAVE ADDRESS
GND GND 1000000
GND VS 1000001
GND SDA 1000010
GND SCL 1000011
VS GND 1000100
VS VS 1000101
VS SDA 1000110
VS SCL 1000111
SDA GND 1001000
SDA VS 1001001
SDA SDA 1001010
SDA SCL 1001011
SCL GND 1001100
SCL VS 1001101
SCL SDA 1001110
SCL SCL 1001111

8.5.4.2 Serial Interface

The INA220 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made by the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The INA220 supports the transmission protocol for fast (1-kHz to 400-kHz) and high-speed (1-kHz to 2.56-MHz) modes. All data bytes are transmitted most significant byte first.

8.5.5 Writing to and Reading from the INA220

Accessing a particular register on the INA220 is accomplished by writing the appropriate value to the register pointer. Refer to Table 2 for a complete list of registers and corresponding addresses. The value for the register pointer, as shown in Figure 18, is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the INA220 requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit LOW. The INA220 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register to which data will be written. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA220 acknowledges receipt of each data byte. The master may terminate data transfer by generating a START or STOP condition.

When reading from the INA220, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA220 retains the register pointer value until it is changed by the next write operation.

Figure 15 and Figure 16 show write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte. Figure 17 shows the timing diagram for the SMBus Alert response operation. Figure 18 shows a typical register pointer configuration.

INA220 ai_tim_wr_word_bos459.gif Figure 15. Timing Diagram for Write Word Format
INA220 ai_tim_rd_word_bos459.gif Figure 16. Timing Diagram for Read Word Format
INA220 ai_tim_smbus_bos459.gif Figure 17. Timing Diagram for SMBus Alert
INA220 ai_tim_typ_pointer_bos459.gif Figure 18. Typical Register Pointer Set

8.5.5.1 High-Speed Two-Wire Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices. The master generates a start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The INA220 does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 2.56-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.56 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. A STOP condition ends the HS-mode and switches all the internal filters of the INA220 to support the F/S mode. See Bus Timing Diagram Definitions and Figure 1 for timing.

8.5.5.2 Power-Up Conditions

Power-up conditions apply to a software reset through the RST bit (bit 15) in the Configuration register, or the I2C bus General Call Reset.

8.6 Register Maps

8.6.1 Register Information

The INA220 uses a bank of registers for holding configuration settings, measurement results, and status information. Table 2 summarizes the INA220 registers; Functional Block Diagram illustrates the registers.

Register contents are updated 4 μs after completion of the write command. Therefore, a 4-μs delay is required between completion of a write to a given register and a subsequent read of that register (without changing the pointer) when using SCL frequencies in excess of 1 MHz.

Table 2. Summary of Register Set

POINTER ADDRESS REGISTER NAME FUNCTION POWER-ON RESET TYPE(1)
HEX BINARY HEX
00 Configuration All-register reset, settings for bus voltage range, PGA gain, ADC resolution/averaging. 00111001 10011111 399F R/W
01 Shunt voltage Shunt voltage measurement data. Shunt voltage — R
02 Bus voltage Bus voltage measurement data. Bus voltage — R
03 Power(2) Power measurement data. 00000000 00000000 0000 R
04 Current(2) Contains the value of the current flowing through the shunt resistor. 00000000 00000000 0000 R
05 Calibration Sets full-scale range and LSB of current and power measurements. Overall system calibration. 00000000 00000000 0000 R/W
(1) Type: R = Read only, R/W = Read/Write.
(2) The Power register and Current register default to 0 because the Calibration register defaults to 0, yielding a zero current value until the Calibration register is programmed.

8.6.2 Register Details

All INA220 registers 16-bit registers are actually two 8-bit bytes through the I2C- or SMBUS-compatible interface.

8.6.2.1 Configuration Register (address = 00h) [reset = 399Fh]

Figure 19. Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST — BRNG PG1 PG0 BADC4 BADC3 BADC2 BADC1 SADC4 SADC3 SADC2 SADC1 MODE3 MODE2 MODE1
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
RST: Reset Bit
Bit 15 Setting this bit to 1 generates a system reset that is the same as power-on reset. Resets all registers to default values; this bit self-clears.
BRNG: Bus Voltage Range
Bit 13 0 = 16-V FSR
1 = 32-V FSR (default value)
PG: PGA (Shunt Voltage Only)
Bits 11, 12 Sets PGA gain and range. Note that the PGA defaults to ÷8 (320-mV range). Table 3 shows the gain and range for the various product gain settings.

Table 3. PG Bit Settings [12:11] (1)

PG1 PG0 GAIN RANGE
0 0 1 ±40 mV
0 1 /2 ±80 mV
1 0 /4 ±160 mV
1 1 /8 ±320 mV
(1) Shaded values are default.
BADC: BADC Bus ADC Resolution/Averaging
Bits 7–10 These bits adjust the Bus ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when averaging results for the Bus Voltage Register (02h).
SADC: SADC Shunt ADC Resolution/Averaging
Bits 3–6 These bits adjust the Shunt ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when averaging results for the Shunt Voltage Register (01h).
BADC (Bus) and SADC (Shunt) ADC resolution/averaging and conversion time settings are shown in Table 4.

Table 4. ADC Settings (SADC [6:3], BADC [10:7])(1)

ADC4 ADC3 ADC2 ADC1 Mode/Samples Conversion Time
0 X(2) 0 0 9-bit 84 μs
0 X(2) 0 1 10-bit 148 μs
0 X(2) 1 0 11-bit 276 μs
0 X(2) 1 1 12-bit 532 μs
1 0 0 0 12-bit 532 μs
1 0 0 1 2 1.06 ms
1 0 1 0 4 2.13 ms
1 0 1 1 8 4.26 ms
1 1 0 0 16 8.51 ms
1 1 0 1 32 17.02 ms
1 1 1 0 64 34.05 ms
1 1 1 1 128 68.10 ms
(1) Shaded values are default.
(2) X = Don't care
MODE: Operating Mode
Bits 0–2 Selects continuous, triggered, or power-down mode of operation. These bits default to continuous shunt and bus measurement mode. The mode settings are shown in Table 5.

Table 5. Mode Settings [2:0](1)

MODE3 MODE2 MODE1 MODE
0 0 0 Power-down
0 0 1 Shunt voltage, triggered
0 1 0 Bus voltage, triggered
0 1 1 Shunt and bus, triggered
1 0 0 ADC off (disabled)
1 0 1 Shunt voltage, continuous
1 1 0 Bus voltage, continuous
1 1 1 Shunt and bus, continuous
(1) Shaded values are default.

8.6.3 Data Output Registers

8.6.3.1 Shunt Voltage Register (address = 01h)

The Shunt Voltage register stores the current shunt voltage reading, VSHUNT. Shunt Voltage register bits are shifted according to the PGA setting selected in the Configuration register (00h). When multiple sign bits are present, they are all the same value. Negative numbers are represented in 2's complement format. Generate the 2's complement of a negative number by complementing the absolute value binary number and adding 1. Extend the sign, denoting a negative number by setting the MSB = 1. Extend the sign to any additional sign bits to form the 16-bit word.

Example: For a value of VSHUNT = –320 mV:

  1. Take the absolute value (include accuracy to 0.01 mV) → 320.00
  2. Translate this number to a whole decimal number → 32000
  3. Convert it to binary → 111 1101 0000 0000
  4. Complement the binary result : 000 0010 1111 1111
  5. Add 1 to the complement to create the 2's-complement formatted result → 000 0011 0000 0000
  6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h (Remember to extend the sign to all sign-bits, as necessary based on the PGA setting.)

At PGA = /8, full-scale range = ±320 mV (decimal = 32000). For VSHUNT = +320 mV, Value = 7D00h; For VSHUNT = –320 mV, Value =8300h; and LSB = 10 μV.

Figure 20. Shunt Voltage Register at PGA = /8
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIGN SD14_8 SD13_8 SD12_8 SD11_8 SD10_8 SD9_8 SD8_8 SD7_8 SD6_8 SD5_8 SD4_8 SD3_8 SD2_8 SD1_8 SD0_8

At PGA = /4, full-scale range = ±160 mV (decimal = 16000). For VSHUNT = +160 mV, Value = 3E80h; For VSHUNT = –160 mV, Value = C180h; and LSB = 10 μV.

Figure 21. Shunt Voltage Register at PGA = /4
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIGN SIGN SD13_4 SD12_4 SD11_4 SD10_4 SD9_4 SD8_4 SD7_4 SD6_4 SD5_4 SD4_4 SD3_4 SD2_4 SD1_4 SD0_4

At PGA = /2, full-scale range = ±80 mV (decimal = 8000). For VSHUNT = +80 mV, Value = 1F40h; For VSHUNT = –80 mV, Value = E0C0h; and LSB = 10 μV.

Figure 22. Shunt Voltage Register at PGA = /2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIGN SIGN SIGN SD12_2 SD11_2 SD10_2 SD9_2 SD8_2 SD7_2 SD6_2 SD5_2 SD4_2 SD3_2 SD2_2 SD1_2 SD0_2

At PGA = /1, full-scale range = ±40 mV (decimal = 4000). For VSHUNT = +40 mV, Value = 0FA0h; For VSHUNT = –40 mV, Value = F060h; and LSB = 10 μV.

Figure 23. Shunt Voltage Register at PGA = /1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIGN SIGN SIGN SIGN SD11_1 SD10_1 SD9_1 SD8_1 SD7_1 SD6_1 SD5_1 SD4_1 SD3_1 SD2_1 SD1_1 SD0_1

Table 6. Shunt Voltage Register Format(1)

VSHUNT Reading (mV) Decimal Value PGA = /8
(D15:D0)		 PGA = /4
(D15:D0)		 PGA = /2
(D15:D0)		 PGA = /1
(D15:D0)
320.02 32002 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
320.01 32001 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
320.00 32000 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
319.99 31999 0111 1100 1111 1111 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
319.98 31998 0111 1100 1111 1110 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
160.02 16002 0011 1110 1000 0010 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
160.01 16001 0011 1110 1000 0001 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
160.00 16000 0011 1110 1000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000
159.99 15999 0011 1110 0111 1111 0011 1110 0111 1111 0001 1111 0100 0000 0000 1111 1010 0000
159.98 15998 0011 1110 0111 1110 0011 1110 0111 1110 0001 1111 0100 0000 0000 1111 1010 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
80.02 8002 0001 1111 0100 0010 0001 1111 0100 0010 0001 1111 0100 0000 0000 1111 1010 0000
80.01 8001 0001 1111 0100 0001 0001 1111 0100 0001 0001 1111 0100 0000 0000 1111 1010 0000
80.00 8000 0001 1111 0100 0000 0001 1111 0100 0000 0001 1111 0100 0000 0000 1111 1010 0000
79.99 7999 0001 1111 0011 1111 0001 1111 0011 1111 0001 1111 0011 1111 0000 1111 1010 0000
79.98 7998 0001 1111 0011 1110 0001 1111 0011 1110 0001 1111 0011 1110 0000 1111 1010 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
40.02 4002 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0000
40.01 4001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0000
40.00 4000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000
39.99 3999 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111
39.98 3998 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
0.02 2 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010
0.01 1 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001
0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
–0.01 –1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
–0.02 –2 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
–39.98 –3998 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010
–39.99 –3999 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001
–40.00 –4000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000
–40.01 –4001 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0110 0000
–40.02 –4002 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0110 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
–79.98 –7998 1110 0000 1100 0010 1110 0000 1100 0010 1110 0000 1100 0010 1111 0000 0110 0000
–79.99 –7999 1110 0000 1100 0001 1110 0000 1100 0001 1110 0000 1100 0001 1111 0000 0110 0000
–80.00 –8000 1110 0000 1100 0000 1110 0000 1100 0000 1110 0000 1100 0000 1111 0000 0110 0000
–80.01 –8001 1110 0000 1011 1111 1110 0000 1011 1111 1110 0000 1100 0000 1111 0000 0110 0000
–80.02 –8002 1110 0000 1011 1110 1110 0000 1011 1110 1110 0000 1100 0000 1111 0000 0110 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
–159.98 –15998 1100 0001 1000 0010 1100 0001 1000 0010 1110 0000 1100 0000 1111 0000 0110 0000
–159.99 –15999 1100 0001 1000 0001 1100 0001 1000 0001 1110 0000 1100 0000 1111 0000 0110 0000
–160.00 –16000 1100 0001 1000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–160.01 –16001 1100 0001 0111 1111 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–160.02 –16002 1100 0001 0111 1110 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif INA220 table_graph_bos459.gif
–319.98 –31998 1000 0011 0000 0010 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–319.99 –31999 1000 0011 0000 0001 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–320.00 –32000 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–320.01 –32001 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
–320.02 –32002 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000
(1) Out-of-range values are shown in gray shading.

8.6.3.2 Bus Voltage Register (address = 02h)

The Bus Voltage register stores the most recent bus voltage reading, VBUS.

At full-scale range = 32 V (decimal = 8000, hex = 1F40), and LSB = 4 mV.

Figure 24. Bus Voltage Register (BRNG = 1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF

At full-scale range = 16 V (decimal = 4000, hex = 0FA0), and LSB = 4 mV.

Figure 25. Bus Voltage Register (BRNG = 0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF
CNVR: Conversion Ready
Bit 1 Although the data from the last conversion can be read at any time, the INA220 Conversion Ready bit (CNVR) indicates when data from a conversion is available in the data output registers. The CNVR bit is set after all conversions, averaging, and multiplications are complete. CNVR will clear under the following conditions:

1.) Writing a new mode into the Operating Mode bits in the Configuration Register (except for Power-Down or Disable)

2.) Reading the Power Register
OVF: Math Overflow Flag
Bit 0 The Math Overflow Flag (OVF) is set when the Power or Current calculations are out of range. It indicates that current and power data may be meaningless.

8.6.3.3 Power Register (address = 03h) [reset = 00h]

Full-scale range and LSB are set by the Calibration register. See Programming the INA220 Calibration Register.

Figure 26. Power Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The Power register records power in watts by multiplying the values of the current with the value of the bus voltage according to the Equation 5:

8.6.3.4 Current Register (address = 04h) [reset =00h]

Full-scale range and LSB depend on the value entered in the Calibration register. See Programming the INA220 Calibration Register. Negative values are stored in 2's complement format.

Figure 27. Current Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The value of the Current register is calculated by multiplying the value in the Shunt Voltage register with the value in the Calibration register according to the Equation 4.

8.6.4 Calibration Register

8.6.4.1 Calibration Register (address = 05h) [reset = 00h]

Current and power calibration are set by bits FS15 to FS1 of the Calibration register. Note that bit FS0 is not used in the calculation. This register sets the current that corresponds to a full-scale drop across the shunt. Full-scale range and the LSB of the current and power measurement depend on the value entered in this register. See the Programming the INA220 Calibration Register. This register is suitable for use in overall system calibration. Note that the 0 POR values are all default.

Figure 28. Calibration Register(1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) FS0 is a void bit and will always be 0. It is not possible to write a 1 to FS0. CALIBRATION is the value stored in FS15:FS1.