JAJSOF5 May   2024 INA4235

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Analog-to-Digital Converter (ADC)
      2. 6.3.2 Internal Measurement and Calculation Engine
      3. 6.3.3 Low Bias Current
      4. 6.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 6.3.5 ALERT Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Versus Triggered Operation
      2. 6.4.2 Device Low Power Modes
      3. 6.4.3 Power-On Reset
      4. 6.4.4 Averaging and Conversion Time Considerations
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 6.5.3 High-Speed I2C Mode
      4. 6.5.4 General Call Reset
      5. 6.5.5 SMBus Alert Response
  8. Register Maps
    1. 7.1 Device Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Filtering and Input Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Registers
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Filtering and Input Considerations

Measuring current is often noisy and such noise can be difficult to define. The INA4235 offers several options for filtering by allowing the conversion times and number of averages to be selected independently in the Configuration register (0h). The conversion times can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility when configuring the monitoring of the power-supply bus.

The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500kHz (±0.5% max) sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling rate harmonics can cause problems. These signals are at 1MHz and higher and can be managed by incorporating filtering at the device input. The high frequency enables the use of low-value series resistors on the filter with negligible effects on measurement accuracy. In general, filtering the device input is only necessary if there are transients at exact harmonics of the 500kHz (±0.5% max) sampling rate (greater than 1MHz). Filter using the lowest possible series resistance (typically 100Ω or less) and a ceramic capacitor. Recommended values for this capacitor are between 0.1µF and 1µF. Figure 8-1 illustrates the device with a filter added at the input.

INA4235 Input
                                        Filtering Figure 8-1 Input Filtering

Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate 26V across the inputs. A large differential scenario can be a short to ground on the load side of the shunt. This type of event can result in the full bus power-supply voltage across the shunt (as long the power supply or energy storage capacitors can support this voltage). Removing a short to ground can result in inductive kickbacks that can exceed the 26V differential and 48V common-mode rating of the device. Inductive kickback voltages are best controlled by Zener-type, transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage capacitance. The Current Shunt Monitor with Transient Robustness Reference Design describes a high-side, current-shunt monitor used to measure the voltage developed across a current-sensing resistor and how to better protect the current-sense device from transient overvoltage conditions.

In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition can result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, and the excessive dV/dt can activate the ESD protection in systems with large currents. Testing demonstrates that the addition of 10Ω resistors in series with each input of the device sufficiently protects against dV/dt failures up to the 48V rating of the device. Selecting these resistors in the range noted has minimal effect on accuracy.