JAJSOF5 May   2024 INA4235

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Analog-to-Digital Converter (ADC)
      2. 6.3.2 Internal Measurement and Calculation Engine
      3. 6.3.3 Low Bias Current
      4. 6.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 6.3.5 ALERT Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Versus Triggered Operation
      2. 6.4.2 Device Low Power Modes
      3. 6.4.3 Power-On Reset
      4. 6.4.4 Averaging and Conversion Time Considerations
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 6.5.3 High-Speed I2C Mode
      4. 6.5.4 General Call Reset
      5. 6.5.5 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Filtering and Input Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Registers
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Timing Requirements (I2C)

MIN NOM MAX UNIT
I2C BUS (FAST MODE)
F(SCL) I2C clock frequency 1 400 kHz
t(BUF) Bus free time between STOP and START conditions 600 ns
t(HDSTA) Hold time after a repeated START condition. After this period, the first clock is generated. 100 ns
t(SUSTA) Repeated START condition setup time 100 ns
t(SUSTO) STOP condition setup time 100 ns
t(HDDAT) Data hold time 10 900 ns
t(SUDAT) Data setup time 100 ns
t(LOW) SCL clock low period 1300 ns
t(HIGH) SCL clock high period 600 ns
tF Data fall time 300 ns
tF Clock fall time 300 ns
tR Clock rise time 300 ns
tR Clock rise time (SCLK ≤ 100 kHz) 1000 ns
I2C BUS (HIGH-SPEED MODE)
F(SCL) I2C clock frequency 10 2940 kHz
t(BUF) Bus free time between STOP and START conditions 160 ns
t(HDSTA) Hold time after a repeated START condition. After this period, the first clock is generated. 100 ns
t(SUSTA) Repeated START condition setup time 100 ns
t(SUSTO) STOP condition setup time 100 ns
t(HDDAT) Data hold time 10 125 ns
t(SUDAT) Data setup time 20 ns
t(LOW) SCL clock low period 200 ns
t(HIGH) SCL clock high period 60 ns
tF Data fall time 80 ns
tF Clock fall time 40 ns
tR Clock rise time 40 ns