JAJSOF3A May 2023 – September 2023 INA700
PRODUCTION DATA
The INA700 operates only as a secondary device on both the SMBus and I2C interfaces. Connections to the bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the communication lines. This noise introduction occurs from capacitive coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielded communication lines reduce the possibility of incorrectly interpreting unintended noise coupling into the digital I/O lines as start or stop commands.
The INA700 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz). All data bytes are transmitted most significant byte (MSB) first and follow the SMBus 3.0 transfer protocol.
To communicate with the INA700, the main device must first address secondary devices through a secondary device address byte. The secondary device address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.
The device has a single address pin, A0. Table 7-2 lists the pin logic levels for each of the four possible addresses. The device samples the state of the address pin on every bus communication. Establish the pin states before any activity on the interface occurs.
A0 | DEVICE ADDRESS |
---|---|
GND | 1000100 |
VS | 1000101 |
SDA | 1000110 |
SCL | 1000111 |