JAJSOF3 データシート

JAJSOF3A May 2023 – September 2023 INA700

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- MXCC018

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7.6.1 INA700 Registers

Table 7-3 lists the INA700 registers. All register locations not listed in Table 7-3 are considered reserved locations and the register contents should not be modified.

Table 7-3 INA700 Registers

Address	Acronym	Register Name	Register Size (bits)	Section
0h	CONFIG	Configuration	16	Go
1h	ADC_CONFIG	ADC Configuration	16	Go
5h	VBUS	Bus Voltage Measurement	16	Go
6h	DIETEMP	Temperature Measurement	16	Go
7h	CURRENT	Current Result	16	Go
8h	POWER	Power Result	24	Go
9h	ENERGY	Energy Result	40	Go
Ah	CHARGE	Charge Result	40	Go
Bh	ALERT_DIAG	Diagnostic Flags and Alert	16	Go
Ch	COL	Current Over-Limit Threshold	16	Go
Dh	CUL	Current Under-Limit Threshold	16	Go
Eh	BOVL	Bus Overvoltage Threshold	16	Go
Fh	BUVL	Bus Undervoltage Threshold	16	Go
10h	TEMP_LIMIT	Temperature Over-Limit Threshold	16	Go
11h	PWR_LIMIT	Power Over-Limit Threshold	16	Go
3Eh	MANUFACTURER_ID	Manufacturer ID	16	Go

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 INA700 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Value can be read only
Write Type
W	W	Value can be written only
Read or Write Type
R/W	R/W	Value can be read or written

7.6.1.1 Configuration (CONFIG) Register (Address = 0h) [reset = 0h]

The CONFIG register is shown in Table 7-5.

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Table 7-5 CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RST	R/W	0h	Reset Bit. Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default values. 0h = Normal Operation 1h = System Reset sets registers to default values This bit self-clears.
14	RSTACC	R/W	0h	Resets the contents of accumulation registers ENERGY and CHARGE to 0 0h = Normal Operation 1h = Clears registers to default values for ENERGY and CHARGE registers
13-6	CONVDLY	R/W	0h	Sets the Delay for initial ADC conversion in steps of 2 ms. 0h = 0 s 1h = 2 ms FFh = 510 ms
5	RESERVED	R	0h	Reserved. Always reads 0.
4	RESERVED	R	1h	Reserved. Always reads 1.
3-0	RESERVED	R	0h	Reserved. Always reads 0.

7.6.1.2 ADC Configuration (ADC_CONFIG) Register (Address = 1h) [reset = FB68h]

The ADC_CONFIG register is shown in Table 7-6.

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Table 7-6 ADC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	MODE	R/W	Fh	The user can set the MODE bits for continuous or triggered mode on bus voltage, current or temperature measurement. 0h = Shutdown 1h = Triggered bus voltage, single shot 2h = Reserved 3h = Reserved 4h = Triggered temperature, single shot 5h = Triggered temperature and bus voltage, single shot 6h = Triggered temperature and current, single shot 7h = Triggered temperature, current and bus voltage, single shot 8h = Shutdown 9h = Continuous bus voltage only Ah = Reserved Bh = Reserved Ch = Continuous temperature only Dh = Continuous bus voltage and temperature Eh = Continuous temperature and current Fh = Continuous temperature, current, and bus voltage
11-9	VBUSCT	R/W	5h	Sets the conversion time of the bus voltage measurement. 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
8-6	VSENCT	R/W	5h	Sets the conversion time of the shunt resistor voltage. Works in conjunction with the temperature conversion time. Total conversion time for a current measurement is the sum of VSENCT and TCT selections. 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
5-3	TCT	R/W	5h	Sets the conversion time of the temperature measurement. Works in conjunction with the shunt voltage conversion time during current measurement. Total conversion time for a current measurement is the sum of VSENCT and TCT selections. 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
2-0	AVG	R/W	0h	Selects ADC sample averaging count. The averaging setting applies to all active inputs. When >0h, the output registers are updated after the averaging is complete. 0h = 1 1h = 4 2h = 16 3h = 64 4h = 128 5h = 256 6h = 512 7h = 1024

7.6.1.3 Bus Voltage Measurement (VBUS) Register (Address = 5h) [reset = 0h]

The VBUS register is shown in Table 7-7.

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Table 7-7 VBUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	VBUS	R	0h	Bus voltage output. (2 value, however always positive. Conversion factor: 3.125 mV/LSB

7.6.1.4 Temperature Measurement (DIETEMP) Register (Address = 6h) [reset = 0h]

The DIETEMP register is shown in Table 7-8.

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Table 7-8 DIETEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DIETEMP	R	0h	Internal die temperature measurement. 2's-complement value. Conversion factor: 125 m°C/LSB

7.6.1.5 Current Result (CURRENT) Register (Address = 7h) [reset = 0h]

The CURRENT register is shown in Table 7-9.

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Table 7-9 CURRENT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CURRENT	R	0h	Calculated current output in Amperes. 2's-complement value. Conversion factor: 480 μA/LSB.

7.6.1.6 Power Result (POWER) Register (Address = 8h) [reset = 0h]

The POWER register is shown in Table 7-10.

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Table 7-10 POWER Register Field Descriptions

Bit	Field	Type	Reset	Description
23-0	POWER	R	0h	Calculated power output. Output value in Watts. Unsigned representation. Positive value. Conversion factor: 96 μW/LSB.

7.6.1.7 Energy Result (ENERGY) Register (Address = 9h) [reset = 0h]

The ENERGY register is shown in Table 7-11.

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Table 7-11 ENERGY Register Field Descriptions

Bit	Field	Type	Reset	Description
39-0	ENERGY	R	0h	Calculated energy output. Output value is in Joules.Unsigned representation. Positive value. Conversion factor: 1.536 mJ/LSB.

7.6.1.8 Charge Result (CHARGE) Register (Address = Ah) [reset = 0h]

The CHARGE register is shown in Table 7-12.

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Table 7-12 CHARGE Register Field Descriptions

Bit	Field	Type	Reset	Description
39-0	CHARGE	R	0h	Calculated charge output. Output value is in Coulombs.2's-complement value. Conversion factor: 30 μC/LSB.

7.6.1.9 Diagnostic Flags and Alert (ALERT_DIAG) Register (Address = Bh) [reset = 0001h]

The ALERT_DIAG register is shown in Table 7-13.

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Table 7-13 ALERT_DIAG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ALATCH	R/W	0h	When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit reset to the idle state when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remain active following a fault until the ALERT_DIAG Register has been read. 0h = Transparent 1h = Latched
14	CNVR	R/W	0h	Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag (bit 1) is asserted, indicating that a conversion cycle is complete. 0h = Disable conversion ready flag on ALERT pin 1h = Enables conversion ready flag on ALERT pin
13	SLOWALERT	R/W	0h	When enabled, ALERT function is asserted on the completed averaged value. This gives the flexibility to delay the ALERT until after the averaged value. 0h = ALERT comparison on non-averaged (ADC) value 1h = ALERT comparison on averaged value
12	APOL	R/W	0h	Alert Polarity bit sets the Alert pin polarity. 0h = Normal (active-low, open-drain) 1h = Inverted (active-high, open-drain)
11	ENERGYOF	R	0h	This bit indicates the health of the ENERGY register. If the 40-bit ENERGY register has overflowed this bit is set to 1. 0h = Normal 1h = Overflow Clears by setting the RSTACC field in the Configuration register.
10	CHARGEOF	R	0h	This bit indicates the health of the CHARGE register. If the 40-bit CHARGE register has overflowed this bit is set to 1. 0h = Normal 1h = Overflow Clears by setting the RSTACC field in the Configuration register.
9	MATHOF	R	0h	This bit is set to 1 if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid. 0h = Normal 1h = Overflow Must be manually cleared by triggering another conversion or by clearing the accumulators with the RSTACC bit.
8	RESERVED	R	0h	Reserved. Always read 0.
7	TMPOL	R	0h	This bit is set to 1 if the temperature measurement exceeds the threshold limit in the temperature over-limit register. 0h = Normal 1h = Overtemperature Event When ALATCH =1 this bit is cleared by reading this register.
6	CURRENTOL	R	0h	This bit is set to 1 if the current measurement exceeds the threshold limit in the current over-limit register. 0h = Normal 1h = Overcurrent Event When ALATCH =1 this bit is cleared by reading this register.
5	CURRENTUL	R	0h	This bit is set to 1 if the current measurement falls below the threshold limit in the shunt under-limit register. 0h = Normal 1h = Undercurrent Event When ALATCH =1 this bit is cleared by reading this register.
4	BUSOL	R	0h	This bit is set to 1 if the bus voltage measurement exceeds the threshold limit in the bus over-limit register. 0h = Normal 1h = Bus Over-Limit Event When ALATCH =1 this bit is cleared by reading this register.
3	BUSUL	R	0h	This bit is set to 1 if the bus voltage measurement falls below the threshold limit in the bus under-limit register. 0h = Normal 1h = Bus Under-Limit Event When ALATCH =1 this bit is cleared by reading this register.
2	POL	R	0h	This bit is set to 1 if the power measurement exceeds the threshold limit in the power limit register. 0h = Normal 1h = Power Over-Limit Event When ALATCH =1 this bit is cleared by reading this register.
1	CNVRF	R	0h	This bit is set to 1 if the conversion is completed. 0h = Normal 1h = Conversion is complete When ALATCH =1 this bit is cleared by reading this register or starting a new triggered conversion.
0	MEMSTAT	R	1h	This bit is set to 0 if a checksum error is detected in the device trim memory space. 0h = Memory Checksum Error 1h = Normal Operation

7.6.1.10 Current Over-Limit Threshold (COL) Register (Address = Ch) [reset = 7FFFh]

If negative values are entered in this register, then a current measurement of 0 A will trip this alarm. When using negative values for the under current and overcurrent thresholds be aware that the overcurrent threshold must be set to the larger (that is, less negative) of the two values. The COL register is shown in Table 7-14.

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Table 7-14 COL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	COL	R/W	7FFFh	Sets the threshold for comparison of the value to detect overcurrent condition (overcurrent protection). 2's-complement value.

7.6.1.11 Current Under-Limit Threshold (CUL) Register (Address = Dh) [reset = 8000h]

The CUL register is shown in Table 7-15.

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Table 7-15 CUL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CUL	R/W	8000h	Sets the threshold for comparison of the value to detect undercurrent condition. 2's-complement value.

7.6.1.12 Bus Overvoltage Threshold (BOVL) Register (Address = Eh) [reset = 7FFFh]

The BOVL register is shown in Table 7-16.

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Table 7-16 BOVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R	0h	Reserved. Always reads 0.
14-0	BOVL	R/W	7FFFh	Sets the threshold for comparison of the value to detect Bus Overvoltage (overvoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.13 Bus Undervoltage Threshold (BUVL) Register (Address = Fh) [reset = 0h]

The BUVL register is shown in Table 7-16.

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Table 7-17 BUVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R	0h	Reserved. Always reads 0.
14-0	BUVL	R/W	0h	Sets the threshold for comparison of the value to detect Bus Undervoltage (undervoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.14 Temperature Over-Limit Threshold (TEMP_LIMIT) Register (Address = 10h) [reset = 7FFFh]

The TEMP_LIMIT register is shown in Table 7-18.

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Table 7-18 TEMP_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TOL	R/W	7FFFh	Sets the threshold for comparison of the value to detect overtemperature measurements. 2's-complement value. The value entered in this field compares directly against the value from the DIETEMP register to determine if an overtemperature condition exists. Conversion factor: 7.8125 m°C/LSB.

7.6.1.15 Power Over-Limit Threshold (PWR_LIMIT) Register (Address = 11h) [reset = FFFFh]

The PWR_LIMIT register is shown in Table 7-19.

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Table 7-19 PWR_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	POL	R/W	FFFFh	Sets the threshold for comparison of the value to detect power over-limit measurements. Unsigned representation, positive value only. The value entered in this field compares directly against the value from the POWER register to determine if an over power condition exists. Conversion factor: 24.576 mW/LSB.

7.6.1.16 Manufacturer ID (MANUFACTURER_ID) Register (Address = 3Eh) [reset = 5449h]

The MANUFACTURER_ID register is shown in Table 7-20.

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Table 7-20 MANUFACTURER_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MANFID	R	5449h	Reads back TI in ASCII.