JAJSLU0A June   2023  – February 2024 ISO1228

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Interface Timing - Non-Daisy Chain
      9. 7.3.9  SPI Interface Timing - Daisy Chain
      10. 7.3.10 SPI Interface Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
          1. 8.2.3.1.1 Current Limit
          2. 8.2.3.1.2 Voltage Thresholds
          3. 8.2.3.1.3 Wire-Break Detection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.9 Electrical Characteristics—DC Specification

(Over recommended operating conditions unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
AVCC (UVLO+) Positive-going UVLO threshold voltage - Sink Mode 7.7 8.4
AVCC (UVLO-) Negative-going UVLO threshold - Sink Mode 5.5 6
AVCC (UVLO+) Positive-going UVLO threshold voltage - Source Mode 11.7 12.5
AVCC (UVLO-) Negative-going UVLO threshold - Source Mode 9 9.8
AVCC (HYS) UVLO threshold hysteresis 1.7
VCC1 (UVLO+) Positive-going UVLO threshold voltage (VCC1) 1.53 1.71 V
VCC1 (UVLO-) Negative-going UVLO threshold (VCC1) 1.3 1.41 V
VCC1 (HYS) UVLO threshold hysteresis (VCC1) 0.08 0.13 V
IAVCC (SINK) AVCC supply quiescent current INx=HIGH or LOW DC 3.5 5 mA
IAVCC (SRC) AVCC supply quiescent current in source mode INx=HIGH or LOW DC 4.5 5.8 mA
IVCC1 VCC1 supply disable current INx=HIGH or LOW DC, OUT_EN = LOW or FLOAT .3 .8 mA
IVCC1 VCC1 supply quiescent current INx=HIGH or LOW DC, OUT_EN = VCC1  3.5 4.3 mA
LOGIC I/O
VIT+ (EN) Positive-going input logic threshold voltage for OUT_EN, SDI, SCLK, COMM_SEL and nCS pins 0.7 × VCC1 V
VIT– (EN) Negative-going input logic threshold voltage for OUT_EN, SDI, SCLK, COMM_SEL and nCS pins 0.3 × VCC1 V
VHYS(EN) Input hysteresis voltage for OUT_EN, SDI, SCLK, COMM_SEL and nCS pins 0.15 × VCC1 V
IIL Low-level input for SDI, SCLK,nRST, BURST_EN and nCS pins OUT_EN = VCC1 and COMM_SEL = VCC1 -15 μA
IIL Low-level input for OUT_EN -30 μA
IIH High-level input for SDI, SCLK, COMM_SEL, nRST, BURST_EN and nCS pins OUT_EN = VCC1 and COMM_SEL = VCC1 15 μA
IIH High-level input for OUT_EN 30 μA
VOH High-level output voltage on OUTx and SDO pins.
VCC1= 1.71 V; IOH = –1 mA		 VCC1 – 0.2 V
VOL Low-level output voltage on OUTx, SDO, nINT and nFAULT pins
VCC1= 1.71 V ; IOH = 1 mA		 0.2 V
CURRENT LIMIT AND WIRE-BREAK
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Sink Type) RTHR = 0 Ω, RILIM = 0 kΩ
VIL < VINx < VIH		 2 3.3 mA
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Sink Type) RTHR = 0 Ω, RILIM = 0kΩ
VIH < VINx < 36		 2.1 3.3 mA
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Sink Type) RTHR = 0 Ω, RILIM = 1 kΩ
VIL < VINx < VIH		 3 4.7 mA
RTHR = 0 Ω, RILIM = 1 kΩ
VIH < VINx < 36 V		 3.1 4.7
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Source Type) RTHR = 0 Ω, RILIM = 1 kΩ
VIL < AVCC - VINx < VIH		 3 4.2 mA
RTHR = 0 Ω, RILIM = 1 kΩ
VIH < AVCC - VINx < 36 V		 3.1 4.2
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Source Type) RTHR = 0 Ω, RILIM = 0 Ω
VIL < AVCC - VINx < VIH		 2 3.3 mA
IINx + I(RPARx) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Source Type) RTHR = 0 Ω, RILIM = 0 Ω
VIH < AVCC - VINx < 36 V		 2.1 3.3 mA
IWB Wire-break Detection Threshold RIWB(1) = 90 kΩ
 		  245 µA
IINx(UVLO) Sum of Current drawn through INx pins and corresponding RPAR external resistor (Sink Type) when AVCC is not present. RILIM = 1 kΩ, RTHR = 0 Ω, RPAR = 9.76kΩ
VINx = 13 V		 1 mA
VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE
VIL Low level threshold voltage at module input (including RTHR) for output low. Sink Type. RILIM = 1 kΩ or 0 Ω,RTHR = 0 Ω 4.7 V
RILIM = 1 kΩ, RTHR = 1 kΩ 7.7
VIL Low level threshold voltage at module input (including RTHR) for output low. Sink Type. RILIM = 0 Ω, RTHR = 1 kΩ 6.7 V
VIH High level threshold voltage at module input (including RTHR) for output high. Sink Type. RILIM = 1 kΩ or 0 Ω, RTHR = 0 Ω 6.4 V
RILIM = 1 kΩ, RTHR = 1 kΩ 11.1
RILIM = 0 Ω, RTHR = 1 kΩ 9.7
VHYS Threshold voltage hysteresis at module input. Sink Type. RILIM = 1 kΩ, RTHR = 0 Ω 0.85 1 V
RILIM = 1 kΩ, RTHR = 1 kΩ 0.8 1
RILIM = 0 Ω, RTHR = 1 kΩ 0.7 1
AVCC-VIL Low level threshold voltage at module input (including RTHR) for output low. Source Type. RILIM = 0 Ω, RTHR = 1.35k Ω 7.4 V
RILIM = 1 kΩ, RTHR = 2 kΩ 10.7 V
AVCC-VIH High level threshold voltage at module input (including RTHR) for output high. Source Type. RILIM = 0 Ω, RTHR = 1.35k Ω 10.9 V
RILIM = 1 kΩ, RTHR = 2 kΩ 14.8 V
VHYS Threshold voltage hysteresis at module input. Source Type. RILIM = 1 kΩ, RTHR = 2 kΩ 0.5 V
RILIM = 0 Ω, RTHR = 1.35k Ω 0.75 1 V
OVER-TEMPERATURE AND THERMAL SHUTDOWN
OTI Over-temperature indication without shutdown (No blocks are shut down) 130 142 150 °C
TSD+ Thermal shutdown turn-on temperature (Field Inputs are tri-stated) 160 180 190 °C
TSD- Thermal shutdown turn-off temperature 155 170 180 °C
TSDHYS Thermal shutdown hysteresis 5 °C
(1) RIWB is the wire break resistance calculated from the equation, RIWB  =   (VINX -2V) /IWB - RTHR