JAJSVB9 September   2024 ISO6163

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5V Supply (±10%)
    10. 5.10 Supply Current Characteristics—5V Supply (±10%)
    11. 5.11 Electrical Characteristics—3.3V Supply (±10%)
    12. 5.12 Supply Current Characteristics—3.3V Supply (±10%)
    13. 5.13 Electrical Characteristics—2.5V Supply (Minimum)
    14. 5.14 Supply Current Characteristics—2.5V Supply  (Minimum)
    15. 5.15 Switching Characteristics—5V Supply (±10%)
    16. 5.16 Switching Characteristics—3.3V Supply (±10%)
    17. 5.17 Switching Characteristics—2.5V Supply (Minimum)
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
      1. 5.19.1 Typical Characteristics: Supply Current ACTIVE state
      2. 5.19.2 Typical Characteristics: High-Speed Channels (ACTIVE state)
      3. 5.19.3 Typical Characteristics: Supply Current STANDBY State
      4. 5.19.4 Typical Characteristics: Low-Speed Control Channels (ACTIVE and STANDBY States)
      5. 5.19.5 Typical Characteristics: Undervoltage Threshold
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Block Diagram
      2. 7.1.2 Feature Description
    2. 7.2 High-Speed Data Channels: A, B, E and F
    3. 7.3 Low-Speed Control Channels With Automatic Enable: C and D
      1. 7.3.1 Low-Speed Control Channels: Timing and Level Details for Automatic Enable
      2. 7.3.2 Low-Speed Control Channels: Considerations if Used for Data
      3. 7.3.3 Low-Speed Control Channels: Considerations During Power Up and Device Reset Events
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

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7.3.1 Low-Speed Control Channels: Timing and Level Details for Automatic Enable

The low-speed control channels with automatic enable have ACTIVE state sample time and delay timer to prevent unintended entry to or exit from STANDBY state. This section explains the impact of these timing requirements on the automatic enable functionality and the maximum data rate possible in the low-speed control channels.

Both low-speed control channels, C and D, have an ACTIVE sample time, tAMS, preventing noise from triggering state transitions. When at least one of the low-speed control channels, C and D, is LOW longer than the ACTIVE sample time, the device generates an ACTIVE mode request and either transitions to ACTIVE state or remains in ACTIVE state, canceling any STANDBY requests that can be generated. When the device must transition from STANDBY to ACTIVE upon an ACTIVE request, the device does so within tLPN from the falling edge on one or both of the low-speed control channels.

When both low-speed control channels have been HIGH longer than the ACTIVE sample time a STANDBY request is generated. As long as an ACTIVE mode request is not generated before the STANDBY state enable delay time, tLP_EN, elapses the device transitions to STANDBY state and remains there until an ACTIVE node request is generated.

The following flowchart and figures show how the ACTIVE sample time, STANDBY state enable delay time and power up conditions impact the state of the device and the high-speed channels.

ISO6163 Low-Speed Control Channel Automatic Enable State Changes Flowchart Figure 7-2 Low-Speed Control Channel Automatic Enable State Changes Flowchart
ISO6163 Low-Speed Control Channel Automatic Enable, Case 1 (ACTIVE to STANDBY Example) Figure 7-3 Low-Speed Control Channel Automatic Enable, Case 1 (ACTIVE to STANDBY Example)
ISO6163 Low-Speed Control Channel Automatic Enable, Case 2 (ACTIVE to STANDBY Example With One Canceled STANDBY Request) Figure 7-4 Low-Speed Control Channel Automatic Enable, Case 2 (ACTIVE to STANDBY Example With One Canceled STANDBY Request)
ISO6163 Low-Speed Control Channel Automatic Enable, Case 3 (STANDBY to ACTIVE Example With One Canceled STANDBY Request) Figure 7-5 Low-Speed Control Channel Automatic Enable, Case 3 (STANDBY to ACTIVE Example With One Canceled STANDBY Request)