SLLS629L January 2006 – October 2015 ISO721 , ISO721M , ISO722 , ISO722M
PRODUCTION DATA.
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Supply voltage | VCC1, VCC2 | –0.5 | 6 | V | |
VI | Input voltage | IN, OUT, or EN | –0.5 | VCC + 0.5(2) | V | |
IO | Output current | ±15 | mA | |||
TJ | Maximum junction temperature | 170 | °C | |||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage(1), VCC1, VCC2 | 3 | 5.5 | V | ||
IOH | Output current | 4 | mA | |||
IOL | –4 | mA | ||||
tui | Input pulse duration | ISO72x | 10 | ns | ||
ISO72xM | 6.67 | |||||
1 / tui | Signaling Rate | ISO72x | 0 | 100 | Mbps | |
ISO72xM | 0 | 150 | ||||
VIH | High-level input voltage (IN, EN) | ISO72x | 2 | 5.5 | V | |
VIL | Low-level input voltage (IN, EN) | 0 | 0.8 | V | ||
VIH | High-level input voltage (IN, EN) | IOS72xM | 0.7 VCC | VCC | V | |
VIL | Low-level input voltage (IN, EN) | 0 | 0.3 VCC | V | ||
TA | Ambient temperature | –40 | 25 | 125 | °C | |
TJ | Junction temperature | See Thermal Information | 150 | °C | ||
H | External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9 certification | 1000 | A/m |
THERMAL METRIC(1) | ISO721 | ISO72x | UNIT | |||
---|---|---|---|---|---|---|
DUB | D | |||||
8 PINS | 8 PINS | |||||
RθJA | Junction-to-ambient thermal resistance | High-K Board | 86.6 | 114.7 | °C/W | |
Low-K Board | N/A | 263 | ||||
RθJC(top) | Junction-to-case (top) thermal resistance | 70.3 | 63 | °C/W | ||
RθJB | Junction-to-board thermal resistance | 50.2 | 54.8 | °C/W | ||
ψJT | Junction-to-top characterization parameter | 34.3 | 18.9 | °C/W | ||
ψJB | Junction-to-board characterization parameter | 49.8 | 54.3 | °C/W | ||
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC1 | VCC1 supply current | Quiescent | VI = VCC or 0 V, no load | 0.5 | 1 | mA | ||
25 Mbps | 2 | 4 | ||||||
ICC2 | VCC2 supply current | ISO722/722M Sleep Mode | VI = VCC or 0 V, No load |
EN at VCC | 200 | μA | ||
Quiescent | EN at 0 V or ISO721/721M |
8 | 12 | mA | ||||
25 Mbps | VI = VCC or 0 V, no load | 10 | 14 | |||||
VOH | High-level output voltage | IOH = –4 mA, See Figure 10 | VCC – 0.8 | 4.6 | V | |||
IOH = –20 μA, See Figure 10 | VCC – 0.1 | 5 | ||||||
VOL | Low-level output voltage | IOL = 4 mA, See Figure 10 | 0.2 | 0.4 | V | |||
IOL = 20 μA, See Figure 10 | 0 | 0.1 | ||||||
VI(HYS) | Input voltage hysteresis | 150 | mV | |||||
IIH | High-level input current | EN, IN at 2 V | 10 | μA | ||||
IIL | Low-level input current | EN, IN at 0.8 V | –10 | |||||
IOZ | High-impedance output current | ISO722, ISO722M | EN, IN at VCC | 1 | μA | |||
CI | Input capacitance to ground | IN at VCC, VI = 0.4 sin (4 × 106πt) | 1 | pF | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V, See Figure 14 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC1 | VCC1 supply current | Quiescent | VI = VCC or 0 V, no load | 0.5 | 1 | mA | ||
25 Mbps | 2 | 4 | ||||||
ICC2 | VCC2 supply current | ISO722/722M Sleep mode |
VI = VCC or 0 V, No load |
EN at VCC | 150 | μA | ||
Quiescent | EN at 0 V or ISO721/721M |
4 | 6.5 | mA | ||||
25 Mbps | VI = VCC or 0 V, no load | 5 | 7.5 | |||||
VOH | High-level output voltage | IOH = –4 mA, See Figure 10 | VCC – 0.4 | 3 | V | |||
IOH = –20 μA, See Figure 10 | VCC – 0.1 | 3.3 | ||||||
VOL | Low-level output voltage | IOL = 4 mA, See Figure 10 | 0.2 | 0.4 | V | |||
IOL = 20 μA, See Figure 10 | 0 | 0.1 | ||||||
VI(HYS) | Input voltage hysteresis | 150 | mV | |||||
IIH | High-level input current | EN, IN at 2 V | 10 | μA | ||||
IIL | Low-level input current | EN, IN at 0.8 V | –10 | μA | ||||
IOZ | High-impedance output current | ISO722, ISO722M | EN, IN at VCC | 1 | μA | |||
CI | Input capacitance to ground | IN at VCC, VI = 0.4 sin (4 × 106πt) | 1 | pF | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V, See Figure 14 | 25 | 40 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC1 | VCC1 supply current | Quiescent | VI = VCC or 0 V, no load | 0.3 | 0.5 | mA | ||
25 Mbps | 1 | 2 | ||||||
ICC2 | VCC2 supply current | ISO722/722M Sleep mode |
VI = VCC or 0 V, No load |
EN at VCC | 200 | μA | ||
Quiescent | EN at 0 V or ISO721/721M |
8 | 12 | mA | ||||
25 Mbps | VI = VCC or 0 V, No load | 10 | 14 | |||||
VOH | High-level output voltage | IOH = –4 mA, See Figure 10 | VCC – 0.8 | 4.6 | V | |||
IOH = –20 μA, See Figure 10 | VCC – 0.1 | 5 | ||||||
VOL | Low-level output voltage | IOL = 4 mA, See Figure 10 | 0.2 | 0.4 | V | |||
IOL = 20 μA, See Figure 10 | 0 | 0.1 | ||||||
VI(HYS) | Input voltage hysteresis | 150 | mV | |||||
IIH | High-level input current | EN, IN at 2 V | 10 | μA | ||||
IIL | Low-level input current | EN, IN at 0.8 V | –10 | μA | ||||
IOZ | High-impedance output current | ISO722, ISO722M | EN, IN at VCC | 1 | μA | |||
CI | Input capacitance to ground | IN at VCC, VI = 0.4 sin (4 × 106πt) | 1 | pF | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V, See Figure 14 | 25 | 40 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC1 | VCC1 supply current | Quiescent | VI = VCC or 0 V, no load | 0.3 | 0.5 | mA | ||
25 Mbps | 1 | 2 | ||||||
ICC2 | VCC2 supply current | ISO722/722M Sleep Mode |
VI = VCC or 0 V, No load |
EN at VCC | 150 | μA | ||
Quiescent | EN at 0 V or ISO721/721M |
4 | 6.5 | mA | ||||
25 Mbps | VI = VCC or 0 V, no load | 5 | 7.5 | |||||
VOH | High-level output voltage | IOH = –4 mA, See Figure 10 | VCC – 0.4 | 3 | V | |||
IOH = –20 μA, See Figure 10 | VCC – 0.1 | 3.3 | ||||||
VOL | Low-level output voltage | IOL = 4 mA, See Figure 10 | 0.2 | 0.4 | V | |||
IOL = 20 μA, See Figure 10 | 0 | 0.1 | ||||||
VI(HYS) | Input voltage hysteresis | 150 | mV | |||||
IIH | High-level input current | EN, IN at 2 V | 10 | μA | ||||
IIL | Low-level input current | EN, IN at 0.8 V | –10 | μA | ||||
IOZ | High-impedance output current | ISO722, ISO722M | EN, IN at VCC | 1 | μA | |||
CI | Input capacitance to ground | IN at VCC, VI = 0.4 sin (4 × 106πt) | 1 | pF | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V, See Figure 14 | 25 | 40 | kV/μs |
PARAMETER | TEST CONDITIONS | ISO721 DUB 8 PINS |
ISO72x D 8 PINS |
UNIT | |||
---|---|---|---|---|---|---|---|
PD | Power Dissipation | ISO72x | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave | 159 | mW | ||
ISO72xM | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave | 195 | mW | ||||
ISO721 | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave | 159 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH | Propagation delay, low-to-high-level output | ISO72x | EN at 0 V, See Figure 10 |
13 | 17 | 24 | ns | |
tPHL | Propagation delay, high-to-low-level output | 13 | 17 | 24 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 2 | ns | ||||
tPLH | Propagation delay, low-to-high-level output | ISO72xM | 8 | 10 | 16 | ns | ||
tPHL | Propagation delay, high-to-low-level output | 8 | 10 | 16 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 1 | ns | ||||
tsk(pp)(1) | Part-to-part skew | 0 | 3 | ns | ||||
tr | Output signal rise time | EN at 0 V, See Figure 10 |
1 | ns | ||||
tf | Output signal fall time | 1 | ||||||
tpHZ | Sleep-mode propagation delay, high-level-to-high-mpedance output |
ISO722 ISO722M |
See Figure 11 | 6 | 8 | 15 | ns | |
tpZH | Sleep-mode propagation delay, high-impedance-to-high-level output |
3.5 | 4 | 8 | μs | |||
tpLZ | Sleep-mode propagation delay, low-level-to-high-impedance output |
See Figure 12 | 5.5 | 8 | 15 | ns | ||
tpZL | Sleep-mode propagation delay, high-impedance-to-low-level output |
4 | 5 | 8 | μs | |||
tfs | Failsafe output delay time from input power loss | See Figure 13 | 3 | μs | ||||
tjit(PP) | Peak-to-peak eye-pattern jitter | ISO72x | 100-Mbps NRZ data input, See Figure 15 | 2 | ns | |||
100-Mbps unrestricted bit run length data input, See Figure 15 | 3 | |||||||
ISO72xM | 150-Mbps NRZ data input, See Figure 15 | 1 | ||||||
150-Mbps unrestricted bit run length data input, See Figure 15 | 2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH | Propagation delay, low-to-high-level output | ISO72x | EN at 0 V, See Figure 10 |
15 | 19 | 30 | ns | |
tPHL | Propagation delay , high-to-low-level output | 15 | 19 | 30 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 3 | ns | ||||
tPLH | Propagation delay, low-to-high-level output | ISO72xM | 10 | 12 | 20 | ns | ||
tPHL | Propagation delay, high-to-low-level output | 10 | 12 | 20 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 1 | ns | ||||
tsk(pp)(1) | Part-to-part skew | 0 | 5 | ns | ||||
tr | Output signal rise time | EN at 0 V, See Figure 10 |
2 | ns | ||||
tf | Output signal fall time | 2 | ns | |||||
tpHZ | Sleep-mode propagation delay, high-level-to-high-mpedance output |
ISO722 ISO722M |
See Figure 11 | 7 | 11 | 25 | ns | |
tpZH | Sleep-mode propagation delay, high-impedance-to-high-level output |
4.5 | 6 | 8 | μs | |||
tpLZ | Sleep-mode propagation delay, low-level-to-high-impedance output |
See Figure 12 | 7 | 13 | 25 | ns | ||
tpZL | Sleep-mode propagation delay, high-impedance-to-low-level output |
4.5 | 6 | 8 | μs | |||
tfs | Failsafe output delay time from input power loss | See Figure 13 | 3 | μs | ||||
tjit(PP) | Peak-to-peak eye-pattern jitter | ISO72x | 100-Mbps NRZ data input, See Figure 15 | 2 | ns | |||
100-Mbps unrestricted bit run length data input, See Figure 15 | 3 | |||||||
ISO72xM | 150-Mbps NRZ data input, See Figure 15 | 1 | ||||||
150-Mbps unrestricted bit run length data input, See Figure 15 | 2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH | Propagation delay, low-to-high-level output | ISO72x | EN at 0 V, See Figure 10 |
15 | 17 | 30 | ns | |
tPHL | Propagation delay , high-to-low-level output | 15 | 17 | 30 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 2 | ns | ||||
tPLH | Propagation delay, low-to-high-level output | ISO72xM | 10 | 12 | 21 | ns | ||
tPHL | Propagation delay, high-to-low-level output | 10 | 12 | 21 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 1 | ns | ||||
tsk(pp)(1) | Part-to-part skew | 0 | 5 | ns | ||||
tr | Output signal rise time | EN at 0 V, See Figure 10 |
1 | ns | ||||
tf | Output signal fall time | 1 | ns | |||||
tpHZ | Sleep-mode propagation delay, high-level-to-high-mpedance output |
ISO722 ISO722M |
See Figure 11 | 7 | 9 | 15 | ns | |
tpZH | Sleep-mode propagation delay, high-impedance-to-high-level output |
4.5 | 5 | 8 | μs | |||
tpLZ | Sleep-mode propagation delay, low-level-to-high-impedance output |
See Figure 12 | 7 | 9 | 15 | ns | ||
tpZL | Sleep-mode propagation delay, high-impedance-to-low-level output |
4.5 | 5 | 8 | μs | |||
tfs | Failsafe output delay time from input power loss | See Figure 13 | 3 | μs | ||||
tjit(PP) | Peak-to-peak eye-pattern jitter | ISO72x | 100-Mbps NRZ data input, See Figure 15 | 2 | ns | |||
100-Mbps unrestricted bit run length data input, See Figure 15 | 3 | |||||||
ISO72xM | 150-Mbps NRZ data input, See Figure 15 | 1 | ||||||
150-Mbps unrestricted bit run length data input, See Figure 15 | 2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
tPLH | Propagation delay, low-to-high-level output | ISO72x | EN at 0 V, See Figure 10 |
17 | 20 | 34 | ns | |
tPHL | Propagation delay , high-to-low-level output | 17 | 20 | 34 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 3 | ns | ||||
tPLH | Propagation delay, low-to-high-level output | ISO72xM | 10 | 12 | 25 | ns | ||
tPHL | Propagation delay, high-to-low-level output | 10 | 12 | 25 | ns | |||
tsk(p) | Pulse skew |tPHL – tPLH| | 0.5 | 1 | ns | ||||
tsk(pp)(1) | Part-to-part skew | 0 | 5 | ns | ||||
tr | Output signal rise time | EN at 0 V, See Figure 10 |
2 | ns | ||||
tf | Output signal fall time | 2 | ||||||
tpHZ | Sleep-mode propagation delay, high-level-to-high-mpedance output |
ISO722 ISO722M |
See Figure 11 | 7 | 13 | 25 | ns | |
tpZH | Sleep-mode propagation delay, high-impedance-to-high-level output |
5 | 6 | 8 | µs | |||
tpLZ | Sleep-mode propagation delay, low-level-to-high-impedance output |
See Figure 12 | 7 | 13 | 25 | ns | ||
tpZL | Sleep-mode propagation delay, high-impedance-to-low-level output |
5 | 6 | 8 | μs | |||
tfs | Failsafe output delay time from input power loss | See Figure 13 | 3 | μs | ||||
tjit(PP) | Peak-to-peak eye-pattern jitter | ISO72x | 100-Mbps NRZ data input, See Figure 15 | 2 | ns | |||
100-Mbps unrestricted bit run length data input, See Figure 15 | 3 | |||||||
ISO72xM | 150-Mbps NRZ data input, See Figure 15 | 1 | ||||||
150-Mbps unrestricted bit run length data input, See Figure 15 | 2 |