JAJS350L September   2007  – October 2024 ISO7230C , ISO7231C , ISO7231M

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: VCC1 and VCC2 at 3.3 V
    10. 6.10 Electrical Characteristics: VCC1 and VCC2 at 5-V
    11. 6.11 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V
    12. 6.12 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    13. 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V
    14. 6.14 Switching Characteristics: VCC1 and VCC2 at 5-V
    15. 6.15 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V
    16. 6.16 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. 9.2.3.1 Insulation Characteristics Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PCB Material
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

ISO7230C ISO7231C ISO7231M Switching Characteristic Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. The 50-Ω is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1 Switching Characteristic Test Circuit and Voltage Waveforms
ISO7230C ISO7231C ISO7231M Enable/Disable Propagation Delay Time Test Circuit and Waveform
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-2 Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7230C ISO7231C ISO7231M Failsafe Delay Time Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-3 Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7230C ISO7231C ISO7231M Common-Mode Transient Immunity Test Circuit
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-4 Common-Mode Transient Immunity Test Circuit
ISO7230C ISO7231C ISO7231M Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s.
Figure 7-5 Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform