SLLS868U September   2007  – October 2024 ISO7240C , ISO7240CF , ISO7240M , ISO7241C , ISO7241M , ISO7242C , ISO7242M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
    10. 5.10 Supply Current Characteristics: VCC1 and VCC2 at 5-V Operation
    11. 5.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 5.12 Supply Current Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    13. 5.13 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    14. 5.14 Supply Current Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 5.15 Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
    16. 5.16 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V Operation
    17. 5.17 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
    18. 5.18 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    19. 5.19 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
    20. 5.20 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    21. 5.21 Insulation Characteristics Curves
    22. 5.22 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Isolated Data Acquisition System for Process Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Isolated SPI for an Analog Input Module with 16 Inputs
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Isolated RS-232 Interface
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air 8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) 0.008 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0884-17); IEC 60112 ≥ 400 V
Material group II
Overvoltage Category Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17):(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 560 VPK
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 x VIOTM, t= 1 s (100% production) 		4000 VPK
qpd Apparent charge(3) Method a: After I/O safety test subgroup 2/3.
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s,		 ≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.3 × VIORM , tm = 10 s,		 ≤5
Method b1: At routine test (100% production) 
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM , tm = 1 s,		 ≤5
CIO Barrier capacitance, input to output(4) VI = 0.4  sin (2πft), f = 1 MHz 2 pF
RIO Isolation resistance, input to output(4) VIO = 500 V, TA = 25°C > 1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011
VIO = 500 V at TS = 150°C >109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production) 2500 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device