SLLSEK9B January   2015  – April 2015 ISO7330C , ISO7330FC , ISO7331C , ISO7331FC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. 8.3.1.1 Package Insulation Specifications
        2. 8.3.1.2 Insulation Characteristics
        3. 8.3.1.3 Regulatory Information
        4. 8.3.1.4 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Typical Supply Current Equations
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Performance Curves
      4. 9.2.4 Systems Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 PCB Material
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage(2) VCC1 , VCC2 –0.5 6 V
Voltage (2) INx, OUTx, ENx –0.5 VCC+0.5(3) V
Output current, IO ±15 mA
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
VESD Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC1, VCC2 Supply voltage 3 5.5 V
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
tui Input pulse duration 40 ns
1 / tui Signaling rate 0 25 Mbps
TJ(1) Junction temperature 136 °C
TA Ambient temperature -40 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.

6.4 Thermal Information

THERMAL METRIC(1) DW PACKAGE UNIT
(16) PINS
RθJA Junction-to-ambient thermal resistance 78.3 °C/W
RθJCtop Junction-to-case (top) thermal resistance 40.9
RθJB Junction-to-board thermal resistance 42.9
ψJT Junction-to-top characterization parameter 15.3
ψJB Junction-to-board characterization parameter 42.4
RθJCbot Junction-to-case (bottom) thermal resistance N/A
PD (ISO7330) Maximum Power Dissipation by ISO7330 VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave 70 mW
PD1 (ISO7330) Maximum Power Dissipation by Side-1 of ISO7330 20
PD2 (ISO7330) Maximum Power Dissipation by Side-2 of ISO7330 50
PD (ISO7331) Maximum Power Dissipation by ISO7331 VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave 84 mW
PD1 (ISO7331) Maximum Power Dissipation by Side-1 of ISO7331 35
PD2 (ISO7331) Maximum Power Dissipation by Side-2 of ISO7331 49
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1)– 0.5 4.7 V
IOH = –20 μA; see Figure 11 VCCO(1) – 0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 480 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input current IN = 0 V –10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14. 25 70 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7330
ICC1 Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V,
EN = 0 V		 0.5 1.1 mA
ICC2 0.4 0.9
ICC1 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF		 0.5 1.1
ICC2 2.6 4.2
ICC1 10 Mbps CL = 15pF 1.1 1.9
ICC2 4.3 6
ICC1 25 Mbps CL = 15pF 2.1 3.3
ICC2 7 9.3
ISO7331
ICC1 Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V,
EN1 = EN2 = 0 V		 0.7 1.6 mA
ICC2 0.7 1.3
ICC1 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF		 1.8 3
ICC2 2.4 3.6
ICC1 10 Mbps CL = 15pF 2.8 4.1
ICC2 3.8 5.1
ICC1 25 Mbps CL = 15pF 4.3 6.2
ICC2 5.8 7.8
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.6 Electrical Characteristics

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1)– 0.5 3 V
IOH = –20 μA; see Figure 11 VCCO(1)– 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 425 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input curre IN = 0 V -10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14 25 50 kV/μs
SUPPLY CURRENT(All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7330
ICC1 Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V,
EN = 0 V		 0.3 0.6 mA
ICC2 0.3 0.6
ICC1 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF		 0.3 0.6
ICC2 2 3.1
ICC1 10 Mbps CL = 15pF 0.7 1.1
ICC2 3.1 4.3
ICC1 25 Mbps CL = 15pF 1.2 2
ICC2 4.8 6.3
ISO7331
ICC1 Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V,
EN = 0 V		 0.5 0.9 mA
ICC2 0.5 0.8
ICC1 DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF		 1.3 2.1
ICC2 1.7 2.6
ICC1 10 Mbps CL = 15pF 1.9 2.7
ICC2 2.6 3.5
ICC1 25 Mbps CL = 15pF 2.9 4.2
ICC2 3.9 5.2
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.7 Switching Characteristics

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 20 32 58 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 4 ns
tsk(o)(2) Channel-to-channel output skew time Same direction channels 2.5 ns
Opposite direction channels 17
tsk(pp)(3) Part-to-part skew time 23 ns
tr Output signal rise time See Figure 11 3 ns
tf Output signal fall time 2 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 7 12 ns
tPLZ Disable propagation delay, low-to-high impedance output 7 12
tPZH Enable propagation delay, high impedance-to-high output ISO733xC 7 12
ISO733xFC 11000 23000(4)
tPZL Enable propagation delay, high impedance-to-low output ISO733xC 11000 23000(4)
ISO733xFC 7 12
tfs Fail-safe output delay time from input power loss See Figure 13 7 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 43 Kbps

6.8 Switching Characteristics

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 22 36 66 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2.5 ns
tsk(o)(2) Channel-to-channel output skew time Same direction channels 3 ns
Opposite direction channels 16
tsk(pp)(3) Part-to-part skew time 27 ns
tr Output signal rise time See Figure 11 3 ns
tf Output signal fall time 2 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 9 18 ns
tPLZ Disable propagation delay, low-to-high impedance output 9 18
tPZH Enable propagation delay, high impedance-to-high output ISO733xC 9 18
ISO733xFC 13000 24000(4)
tPZL Enable propagation delay, high impedance-to-low output ISO733xC 13000 24000(4)
ISO733xFC 9 18
tfs Fail-safe output delay time from input power loss See Figure 13 7 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 41 Kbps

6.9 Typical Characteristics

ISO7330C ISO7330FC ISO7331C ISO7331FC D001_SLLSEK9.gif
TA = 25°C CL = 15 pF
Figure 1. ISO7330 Supply Current vs Data Rate
(with 15 pF Load)
ISO7330C ISO7330FC ISO7331C ISO7331FC D003_SLLSEK9.gif
TA = 25°C CL = 15 pF
Figure 3. ISO7331 Supply Current vs Data Rate
(with 15 pF Load)
ISO7330C ISO7330FC ISO7331C ISO7331FC D005_SLLSEK9.gif
TA = 25°C
Figure 5. High-Level Output Voltage vs High-level Output Current
ISO7330C ISO7330FC ISO7331C ISO7331FC D007_SLLSEK9.gif
Figure 7. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7330C ISO7330FC ISO7331C ISO7331FC D009_SLLSEK9.gif
Figure 9. Input Glitch Suppression Time vs Free-Air Temperature
ISO7330C ISO7330FC ISO7331C ISO7331FC D002_SLLSEK9.gif
TA = 25°C CL = No Load
Figure 2. ISO7330 Supply Current vs Data Rate
(with No Load)
ISO7330C ISO7330FC ISO7331C ISO7331FC D004_SLLSEK9.gif
TA = 25°C CL = No Load
Figure 4. ISO7331 Supply Current vs Data Rate
(with No Load)
ISO7330C ISO7330FC ISO7331C ISO7331FC D006_SLLSEK9.gif
TA = 25°C
Figure 6. Low-Level Output Voltage vs Low-Level Output Current
ISO7330C ISO7330FC ISO7331C ISO7331FC D008_SLLSEK9.gif
Figure 8. Propagation Delay Time vs Free-Air Temperature
ISO7330C ISO7330FC ISO7331C ISO7331FC D010_SLLSEK9.gif
TA = 25°C
Figure 10. Output Jitter vs Data Rate