SLLSEK5B July   2015  – May 2017 ISO7340-Q1 , ISO7341-Q1 , ISO7342-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V Supply
    10. 7.10 Supply Current Characteristics—5-V Supply
    11. 7.11 Electrical Characteristics—3.3-V Supply
    12. 7.12 Supply Current Characteristics—3.3-V Supply
    13. 7.13 Switching Characteristics—5-V Supply
    14. 7.14 Switching Characteristics—3.3-V Supply
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Isolated Data Acquisition System for Process Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Typical Supply Current Equations
            1. 10.2.1.2.1.1 ISO7340-Q1
            2. 10.2.1.2.1.2 ISO7341-Q1
            3. 10.2.1.2.1.3 ISO7342-Q1
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application for Module With 16 Inputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Typical Application for RS-232 Interface
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9 Detailed Description

9.1 Overview

The isolator in Figure 18 is based on a capacitive isolation-barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.

In principle, a single-ended input signal entering the HF channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can be either above or below the common-mode voltage VREF depending on whether the input bit transitioned from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL) at the output of the HF channel comparator measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

9.2 Functional Block Diagram

ISO7340-Q1 ISO7341-Q1 ISO7342-Q1 internal_block_sllsei6.gif Figure 18. Conceptual Block Diagram of a Digital Capacitive Isolator

9.3 Feature Description

The ISO734x-Q1 family of devices are available in multiple channel configurations and default output state options to enable wide variety of application uses.

ORDERABLE DEVICE CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7340CQDWQ1 and ISO7340CQDWRQ1 4 Forward,
0 Reverse		 3000 VRMS / 4242 VPK(1) 25 Mbps High
ISO7340FCQDWQ1 and ISO7340FCQDWRQ1 Low
ISO7341CQDWQ1 and ISO7341CQDWRQ1 3 Forward,
1 Reverse		 High
ISO7341FCQDWQ1 and ISO7341FCQDWRQ1 Low
ISO7342CQDWQ1 and ISO7342CQDWRQ1 2 Forward,
2 Reverse		 High
ISO7342FCQDWQ1 and ISO7342FCQDWRQ1 Low
(1) See the Safety-Related Certifications section for detailed isolation ratings.

9.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO734x-Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

9.4 Device Functional Modes

Table 1 lists the functional modes for the ISO734x-Q1 family of devices.

Table 1. Function Table(1)

VCCI VCCO INPUT
(INx)		 OUTPUT ENABLE
(ENx)		 OUTPUT
(OUTx)
ISO734xCQDWQ1 AND ISO734xCQDWRQ1 ISO734xFCQDWQ1 AND ISO734xFCQDWRQ1
PU PU H H or Open H H
L H or Open L L
X L Z Z
Open H or Open H(2) L(3)
PD PU X H or Open H(2) L(3)
X PU X L Z Z
X PD X X Undetermined Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level

9.4.1 Device I/O Schematics

ISO7340-Q1 ISO7341-Q1 ISO7342-Q1 device_IO_sllsei6.gif Figure 19. Device I/O Schematics