JAJSH14C March   2012  – March 2019 ISO7421E-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 Pin Configuration and Functions
    1. Table 1. Pin Functions
  5. 5 静電気放電に関する注意事項
    1.     Device Images
      1. 5.1 Device Function Table
      2. 5.2 Available Options
  6. 6 Absolute Maximum Ratings
  7. 7 Thermal Information
  8. 8 Recommended Operating Conditions
  9. 9 Electrical Characteristics
  10. 10Switching Characteristics
  11. 11Electrical Characteristics
  12. 12Switching Characteristics
  13. 13Electrical Characteristics
  14. 14Switching Characteristics
  15. 15Electrical Characteristics
  16. 16Switching Characteristics
  17. 17Parameter Measurement Information
  18. 18Device Information
    1. 18.1 Package Characteristics
    2. 18.2 IEC 60664-1 Ratings Table
    3. 18.3 Insulation Characteristics
    4. 18.4 Regulatory Information
    5. 18.5 IEC Safety Limiting Values
    6. 18.6 Equivalent Input And Output Schematic Diagrams
  19. 19Typical Characteristics
  20. 20Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

17 Parameter Measurement Information

ISO7421E-Q1 switch_test_circuit_slls984.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3ns, tf ≤ 3ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
ISO7421E-Q1 fail_safe_lls984.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7421E-Q1 com_tran_imm_test_circ_slls984.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit