JAJSH14C March   2012  – March 2019 ISO7421E-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 Pin Configuration and Functions
    1. Table 1. Pin Functions
  5. 5 静電気放電に関する注意事項
    1.     Device Images
      1. 5.1 Device Function Table
      2. 5.2 Available Options
  6. 6 Absolute Maximum Ratings
  7. 7 Thermal Information
  8. 8 Recommended Operating Conditions
  9. 9 Electrical Characteristics
  10. 10Switching Characteristics
  11. 11Electrical Characteristics
  12. 12Switching Characteristics
  13. 13Electrical Characteristics
  14. 14Switching Characteristics
  15. 15Electrical Characteristics
  16. 16Switching Characteristics
  17. 17Parameter Measurement Information
  18. 18Device Information
    1. 18.1 Package Characteristics
    2. 18.2 IEC 60664-1 Ratings Table
    3. 18.3 Insulation Characteristics
    4. 18.4 Regulatory Information
    5. 18.5 IEC Safety Limiting Values
    6. 18.6 Equivalent Input And Output Schematic Diagrams
  19. 19Typical Characteristics
  20. 20Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

18.1 Package Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance through air 7.6 mm
L(I02) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface 7.6 mm
CTI Tracking resistance (Comparative Tracking Index) DIN EN 60112 (VDE 0303-11) ≥400 V
Minimum internal gap (Internal Clearance) Distance through the insulation 0.014 mm
RIO Isolation resistance, input to output(1) Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device >1012 Ω
CIO Barrier capacitance input to output(1) VIO = 0.4 sin(2πft), f = 1 MHz 2 pF
CI Input capacitance to ground(2) VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.

empty para for space above the NOTE

NOTE

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance

Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.