SLLSEU0G November   2016  – October 2024 ISO7740-Q1 , ISO7741-Q1 , ISO7742-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5-V Supply
    10. 5.10 Supply Current Characteristics—5-V Supply
    11. 5.11 Electrical Characteristics—3.3-V Supply
    12. 5.12 Supply Current Characteristics—3.3-V Supply
    13. 5.13 Electrical Characteristics—2.5-V Supply 
    14. 5.14 Supply Current Characteristics—2.5-V Supply
    15. 5.15 Switching Characteristics—5-V Supply
    16. 5.16 Switching Characteristics—3.3-V Supply
    17. 5.17 Switching Characteristics—2.5-V Supply
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
        1. 8.2.3.1 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBQ|16
  • DWW|16
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 8-8). Layer stacking must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links typically have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep the planes symmetrical. This makes the stack mechanically stable and prevents warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide.