JAJSUN8I November   2014  – November 2024 ISO7841

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5V Supply
    10. 5.10 Supply Current Characteristics—5V Supply
    11. 5.11 Electrical Characteristics—3.3V Supply
    12. 5.12 Supply Current Characteristics—3.3V Supply
    13. 5.13 Electrical Characteristics—2.5V Supply
    14. 5.14 Supply Current Characteristics—2.5V Supply
    15. 5.15 Switching Characteristics—5V Supply
    16. 5.16 Switching Characteristics—3.3V Supply
    17. 5.17 Switching Characteristics—2.5V Supply
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWW|16
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
DWDWW
GENERAL
CLRExternal clearance(1)Shortest pin-to-pin distance through air>8>14.5mm
Shortest pin-to-pin distance through air (typical) 15.0 mm
CPGExternal creepage(1)Shortest pin-to-pin distance across the package surface>8>14.5mm
Shortest pin-to-pin distance across the package surface (typical) 15.0 mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>21>21μm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A>600>600V
Material groupII
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600VRMSI–IVI–IV
Rated mains voltage ≤ 1000VRMSI–IIII–IV
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORMMaximum repetitive peak isolation voltage21212828VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); Time dependent dielectric breakdown (TDDB) Test, see Figure 5-1 and Figure 5-215002000VRMS
DC voltage21212828VDC
VIOTMMaximum transient isolation voltageVTEST = 1.2 × VIOTM
t = 60s (qualification)
t= 1s (100% production)		80008000VPK
VIMP Maximum impulse voltage (3) Tested in air, 1.2/50μs waveform per IEC 62368-1 9800 9800 VPK
VIOSMMaximum surge isolation voltage (4)VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-11280012800VPK
qpdApparent charge (5)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIOTM = 2545VPK (DW) and 3394VPK (DWW), tm = 10s		≤5≤5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 × VIORM = 3394VPK (DW) and 4525VPK (DWW), tm = 10s		≤5≤5

Method b: At routine test (100% production);

Vini = 1.2 x VIOTM, tini = 1s;

Vpd(m) = 1.875 x VIORM, tm = 1s (method b1) or

Vpd(m) = Vini, tm = tini (method b2)

≤5≤5
CIOBarrier capacitance, input to output(6)VIO = 0.4 × sin (2πft), f = 1MHz22pF
RIOIsolation resistance, input to output (6)VIO = 500V, TA = 25°C>1012>1012Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C>1011>1011
VIO = 500V at TS = 150°C>109>109
Pollution degree22
Climatic category55/125/2155/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700VRMS, t = 60s (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1s (100% production)		57005700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.