JAJSLI4A May 2021 – December 2021 ISOW1044
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIO | Logic supply voltage | 1.8-V operation | 1.71 | 1.89 | V | |
2.5-V, 3.3-V, and 5.5-V operation | 2.25 | 5.5 | ||||
VDD | Power converter supply voltage | 4.5 | 5.5 | V | ||
VDD(UVLO+) | Supply threshold when Power converter supply is rising | 2.7 | 2.95 | V | ||
VDD(UVLO-) | Supply threshold when Power converter supply is falling | 2.40 | 2.55 | V | ||
VHYS1(UVLO) | Power converter supply voltage hysteresis | 0.15 | 0.24 | V | ||
VIO(UVLO+) | Rising threshold of Logic supply voltage | 1.7 | V | |||
VIO(UVLO-) | Falling threshold of Logic supply voltage | 1 | V | |||
VHYS2(UVLO) | Logic supply voltage hysteresis | 75 | 125 | mV | ||
VIH | High-level input voltage (TXD, STB, EN, and IN inputs) | 0.7 × VIO | VIO | V | ||
VIL | Low-level input voltage (TXD, STB, EN, and IN inputs) | 0 | 0.3 × VIO | V | ||
IOH | High-level output current RXD | VIO = 5V | -4 | mA | ||
VIO = 3.3V | -2 | mA | ||||
VIO = 1.8 or 2.5V | -1 | mA | ||||
IOL | Low-level output current RXD | VIO = 5V | 4 | mA | ||
VIO = 3.3V | 2 | mA | ||||
VIO = 1.8 or 2.5V | 1 | mA | ||||
IOH | High-level output current OUT | VDD=4.5 to 5.5V | -4 | mA | ||
IOL | Low-level output current OUT | VDD=4.5 to 5.5V | 4 | mA | ||
1/tUI | Signaling rate | CAN | 5 | Mbps | ||
DR | Data rate for extra GPIO channel | GPIO | 10 | Mbps | ||
Tpwrup | Power up time after applying input supply(Isolated output supply reaches 90% of setpoint and data transmission can start after this) | 5 | ms | |||
TA | Ambient operating temperature | ≤ 50% of bits are dominant | –40 | 125 | °C | |
–40 | 105 | °C |