A low cost two layer PCB should be sufficient to achieve good EMC performance:

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in².
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the device from rising to unacceptable levels.

Figure 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must be followed to meet application EMC requirements:

• High frequency bypass capacitors 10 nF must be placed close to V_DD and V_ISOOUT pins, less than 1 mm distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure that these capacitors are 0402 size so that they offer least inductance (ESL).
• Bulk capacitors of atleast 10 μF must be placed on power converter input (V_DD) and output (V_ISOOUT) supply pins.
• Traces on V_DD and GND1 must be symmetric till bypass capacitors. Similarly traces on V_ISOOUT and GND2 must be symmetric.
• Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on V_ISOOUT and GND2 path so that any high frequency noise from power converter output sees a high impedance before it goes to other components on PCB.
• Do not have any metal traces or ground pour within 4 mm of power converter output terminals V_ISOOUT pin12 and GND2 pin11. VSEL pin is also in V_ISOOUT domain and should be shorted to either pin 11 or pin 12 for output voltage selection.
• Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated emissions design.