JAJSET7C May   2017  – October 2018 IWR1443

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1  Power Supply Sequencing and Reset Timing
      2. 5.9.2  Synchronized Frame Triggering
      3. 5.9.3  Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
        2. 5.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.9.4.3 SPI Slave Mode I/O Timings
          1. Table 5-11 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5  LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6  General-Purpose Input/Output
        1. Table 5-13 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7  Controller Area Network Interface (DCAN)
        1. Table 5-14 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 5.9.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.9.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.9.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.9.11 JTAG Interface
        1. Table 5-20 JTAG Timing Conditions
        2. Table 5-21 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-22 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
      12. 5.9.12 Camera Serial Interface (CSI)
        1. Table 5-23 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 External Interfaces
    4. 6.4 Subsystems
      1. 6.4.1 RF and Analog Subsystem
        1. 6.4.1.1 Clock Subsystem
        2. 6.4.1.2 Transmit Subsystem
        3. 6.4.1.3 Receive Subsystem
        4. 6.4.1.4 Radio Processor Subsystem
      2. 6.4.2 Master (Control) System
      3. 6.4.3 Host Interface
    5. 6.5 Accelerators and Coprocessors
    6. 6.6 Other Subsystems
      1. 6.6.1 A2D Data Format Over CSI2 Interface
      2. 6.6.2 ADC Channels (Service) for User Application
        1. Table 6-2 GP-ADC Parameter
    7. 6.7 Identification
    8. 6.8 Boot Modes
      1. 6.8.1 Flashing Mode
      2. 6.8.2 Functional Mode
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

Changes from February 20, 2018 to October 31, 2018 (from B Revision (February 2018) to C Revision)

  • RXノイズ指数を「15dB (76～77GHz)」から「14dB (76～77GHz)」に更新Go
  • RXノイズ指数を「16dB (77～81GHz)」から「15dB (77～81GHz)」に更新Go
  • 1MHzでの位相ノイズを「－94dBc/Hz (76～77GHz)」から「－95dBc/Hz (76～77GHz)」に更新Go
  • 1MHzでの位相ノイズを「－91dBc/Hz (77～81GHz)」から「－93dBc/Hz (77～81GHz)」に更新Go
  • 「高速データ・インターフェイス」箇条書き項目から「（中間データ）」を削除Go
  • 外部駆動の発振器、および外部駆動のクロックから、50MHzを削除Go
  • 製品情報を更新Go
  • 「機能ブロック図」からVMOSブロックを削除Go
  • Added table note to "Number of transmitters" in Device Features ComparisonGo
  • Updated IWR1443 and IWR1642 Product status from AI to PDGo
  • Updated OSC_CLKOUTGo
  • Updated P7 from "Open Drain" to "Pull Up'Go
  • Updated B10 DESCRIPTIONGo
  • Updated A10, A13, A2, and B2 DESCRIPTIONGo
  • Removed footnote from Flash programming and RS232 UARTGo
  • Updated ESD RatingsGo
  • Updated/Changed Power-On Hours (POH)Go
  • Updated VIOIN in Recommended Operating ConditionsGo
  • Updated VIL 1.8V MAX from "3*VIOIN" to "0.3*VIOIN"Go
  • Updated VOH in Recommended Operating ConditionsGo
  • Updated VOH in Recommended Operating ConditionsGo
  • Updated Recommended Operating ConditionsGo
  • Added "VNWA" to 1.2 V Supply in Power Supply Rails CharacteristicsGo
  • Completely updated Ripple Specifications tableGo
  • Updated Receiver Noise figure values in RF SpecificationGo
  • Updated Receiver 1-dB compression point value from "–5" to "–8"Go
  • Updated "IQ gain mismatch" to "Image Rejection Ratio (IMRR)"Go
  • Removed IQ phase mismatch from RF SpecificationGo
  • Updated RF Specification tableGo
  • Updated footnote in RF SpecificationGo
  • Removed 1v4 signal from Device Wakeup Go
  • Updated Device Wake-up SequenceGo
  • Updated Synchronized Frame Triggering text Go
  • Added Synchronized Frame Triggering subsectionGo
  • Removed TLag from Frame Trigger Timing table Go
  • Updated Crystal Implementation noteGo
  • Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40"Go
  • Completely updated External Clock Mode SpecificationsGo
  • Updated SPI Slave Mode Timing RequirementsGo
  • Added LVDS Interface ConfigurationGo
  • Updated LVDS Interface Lane Config imageGo
  • Updated Timing ParametersGo
  • Updated LVDS Electrical Characteristics Go
  • Updated Timing Requirements for QSPI Input (Read) TimingsGo
  • Added Q12, Q13, Q14, and Q15 to QSPI Switching CharacteristicsGo
  • Updated Data bit rate from 900 Mbps to 600 MbpsGo
  • Removed TCLK-SETTLE and THS-SETTLEGo
  • Updated Clock Subsystem diagramGo
  • Updated/Changed Transmit Subsystem (Per Channel)Go
  • Removed Master System Memory MapGo
  • Updated Host InterfaceGo
  • Updated text in "A2D Data Format Over CSI2 Interface"Go
  • Updated text in ADC Channels (Service) for User ApplicationGo
  • Completely updated GP-ADC Parameter tableGo
  • Updated text in Functional ModeGo
  • Updated Application InformationGo
  • Updated Device NomenclatureGo