JAJSI63 November   2019 LDC1001-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション — 軸方向距離検出
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inductive Sensing
      2. 7.3.2 Measuring Parallel Resonance Impedance and Inductance With LDC1001-Q1
        1. 7.3.2.1 Measuring Inductance
          1. 7.3.2.1.1 Example
    4. 7.4 Device Functional Modes
      1. 7.4.1 INTB Pin Modes
        1. 7.4.1.1 Comparator Mode
        2. 7.4.1.2 Wake-Up Mode
        3. 7.4.1.3 DRDYB Mode
    5. 7.5 Programming
      1. 7.5.1 Digital Interface
        1. 7.5.1.1 SPI Description
        2. 7.5.1.2 Extended SPI Transactions
    6. 7.6 Register Map
      1. 7.6.1 Register Description
        1. 7.6.1.1  Revision ID (offset = 0x00) [reset = 0x80]
          1. Table 2. Revision ID Field Descriptions
        2. 7.6.1.2  Rp_MAX (offset = 0x01) [reset = 0x0E]
          1. Table 3. Rp_MAX Field Descriptions
        3. 7.6.1.3  Rp_MIN (offset = 0x02) [reset = 0x14]
          1. Table 4. Rp_MIN Field Descriptions
        4. 7.6.1.4  Sensor Frequency (offset = 0x03) [reset = 0x45]
          1. Table 5. Sensor Frequency Field Descriptions
        5. 7.6.1.5  LDC Configuration (offset = 0x04) [reset = 0x1B]
          1. Table 6. LDC Configuration Field Descriptions
        6. 7.6.1.6  Clock Configuration (offset = 0x05) [reset = 0x01]
          1. Table 7. Clock Configuration Field Descriptions
        7. 7.6.1.7  Comparator Threshold High LSB (offset = 0x06) [reset = 0xFF]
          1. Table 8. Comparator Threshold High LSB Field Descriptions
        8. 7.6.1.8  Comparator Threshold High MSB (offset = 0x07) [reset = 0xFF]
          1. Table 9. Comparator Threshold High MSB Field Descriptions
        9. 7.6.1.9  Comparator Threshold Low LSB (offset = 0x08) [reset = 0x00]
          1. Table 10. Comparator Threshold Low LSB Field Descriptions
        10. 7.6.1.10 Comparator Threshold Low MSB (offset = 0x09) [reset = 0x00]
          1. Table 11. Comparator Threshold Low MSB Field Descriptions
        11. 7.6.1.11 INTB Pin Configuration (offset = 0x0A) [reset = 0x00]
          1. Table 12. INTB Pin Configuration Field Descriptions
        12. 7.6.1.12 Power Configuration (offset = 0x0B) [reset = 0x00]
          1. Table 13. Power Configuration Field Descriptions
        13. 7.6.1.13 Status (offset = 0x20) [reset = NA]
          1. Table 14. Status Field Descriptions
        14. 7.6.1.14 Proximity Data LSB (offset = 0x21) [reset = NA]
          1. Table 15. Proximity Data LSB Field Descriptions
        15. 7.6.1.15 Proximity Data MSB (offset = 0x22) [reset = NA]
          1. Table 16. Proximity Data MSB Field Descriptions
        16. 7.6.1.16 Frequency Counter LSB (offset = 0x23) [reset = NA]
          1. Table 17. Frequency Counter LSB Field Descriptions
        17. 7.6.1.17 Frequency Counter Mid-Byte (offset = 0x24) [reset = NA]
          1. Table 18. Frequency Counter Mid-Byte Field Descriptions
        18. 7.6.1.18 Frequency Counter MSB (offset = 0x25) [reset = NA]
          1. Table 19. Frequency Counter MSB Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Calculation of Rp_Min and Rp_Max
        1. 8.1.1.1 Rp_MAX
        2. 8.1.1.2 Rp_MIN
      2. 8.1.2 Output Data Rate
        1. 8.1.2.1 Example
      3. 8.1.3 Selecting a Filter Capacitor (CFA and CFB Pins)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sensor and Target
        2. 8.2.2.2 Calculating a Sensor Capacitor
        3. 8.2.2.3 Selecting a Filter Capacitor
        4. 8.2.2.4 Setting Rp_MIN and Rp_MAX
        5. 8.2.2.5 Calculating Minimum Sensor Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

Unless otherwise noted, all limits specified at TA = 25°C, VDD = 5 V, VIO = 3.3 V, 10-pF capacitive load in parallel with a 10-kΩ load on the SDO. Specified by design; not production tested. See Figure 1
MIN NOM MAX UNIT
fSCLK Serial clock frequency See Figure 1 4 MHz
twH SCLK pulse-width high fSCLK = 4 Mhz, See Figure 1 0.4 / fSCLK s
twL SCLK pulse-width low fSCLK = 4 Mhz, See Figure 1 0.4 / fSCLK s
tsu SDI setup time See Figure 1 10 ns
th SDI hold time 10 ns
tODZ SDO driven-to-tristate time Measured at 10% / 90% point, See Figure 2 20 ns
tOZD SDO tristate-to-driven time Measured at 10% / 90% point, See Figure 2 20 ns
td(OUTPUT) SDO output delay time See Figure 2  20 ns
tsu(CS) CSB setup time 20 ns
th(CS) CSB hold time 20 ns
tIAG inter-access gap See Figure 16 100 ns
tw(DRDY) Data ready pulse width Data ready pulse at every 1 / ODR if no data is read 1 / fsensor s
LDC1001-Q1 td_write_slos886.gifFigure 1. Write Timing Diagram
LDC1001-Q1 td_read_slos886.gifFigure 2. Read Timing Diagram