11.1 Layout Guidelines

The COM pin must be bypassed to ground with an appropriate value capacitor. For details of how to choose the capacitor value, refer to Setting COM Pin Capacitor. C_COM should be placed as close as possible to the COM pin. The COM signal should be tied to a small copper fill placed underneath the INn signals. The INn signals should stay clear of other high frequency traces.

Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor capacitor should be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in Figure 32) should be placed at the appropriate location next to (but not touching) the metal target. The INn traces should be at least 6 mil (0.15 mm) wide to minimize parasitic inductances.

For the DSBGA package, the inner four device pads (INTB, OUT3, LPWRB, and SDA) should be routed out on an inner layer through vias, with the traces offset to reduce coupling with other signals. These four vias may need to use blind vias or microvias to bring the signals out. The PCB layer stack should use a thinner (4 mil or 0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used.

11.2 Layout Example

Figure 32. Layout of LDC2114 (DSBGA-16) With Decoupling Capacitors and Sensor Capacitors

Figure 33. Layout of LDC2114 (TSSOP-16) With Decoupling Capacitors and Sensor Capacitors

11.3 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect.