JAJSSF8 December   2023 LDC5071-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Diagnostics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Supply Voltage
      2. 6.3.2 Excitation Signal
      3. 6.3.3 Signal Processing Block
        1. 6.3.3.1 Demodulation
        2. 6.3.3.2 Fixed Gain Control
        3. 6.3.3.3 Automatic Gain Control
      4. 6.3.4 Output Stage
      5. 6.3.5 Diagnostics
        1. 6.3.5.1 Undervoltage Diagnostics
        2. 6.3.5.2 Initialization Diagnostics
        3. 6.3.5.3 Normal State Diagnostics
        4. 6.3.5.4 Fault State Diagnostics
    4. 6.4 Device Functional Modes
      1. 6.4.1 IDLE State
      2. 6.4.2 DIAGNOSTICS State
      3. 6.4.3 NORMAL State
      4. 6.4.4 FAULT State
      5. 6.4.5 DISABLED State
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 5-V Supply Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VREG and VCC
          2. 7.2.1.2.2 Output Capacitors
          3. 7.2.1.2.3 Automatic Gain Control (AGC) Mode
        3. 7.2.1.3 Application Curve
      2. 7.2.2 3.3-V Supply Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 VREG and VCC
          2. 7.2.2.2.2 Output Capacitors
          3. 7.2.2.2.3 Fixed Gain Mode
      3. 7.2.3 Redundancy Mode
      4. 7.2.4 Single-Ended Mode
      5. 7.2.5 External Diagnostics Required for Loss of VCC or GND
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Mode 1: VCC = 5 V, VREG = 3.3 V
      2. 7.3.2 Mode 2: VCC = VREG = 3.3 V
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.2.2.2.3 Fixed Gain Mode

Some cases can use fixed gain mode where the variation in INx amplitudes between boards is sufficiently small and the air gap is well controlled. One advantage to fixed gain mode is that changes in OUTx amplitudes can be measured by the host MCU. This could lead to information about air gap variance. One disadvantage to fixed gain mode is that the signal path gain will not adjust due to variances, which could lead to saturation if the signal is too large, or lead to increased error due to low SNR if the signal is too small.

To use fixed gain mode, first determine the maximum amplitude of the signal at the INx inputs. This is calculated by knowing the maximum coupling coefficient between the LC exciter coil and the Sin/Cos coils (see Equation 10 and Equation 11).

Equation 10. GUID-8DA261CA-E3BC-4B0C-96E8-EAD735BA87C2-low.gif

where

  • VAMP_INx= differential voltage on the INx pin
  • VAMP_LC= differential voltage on LCOUT
  • kcoupling= coupling coefficient between exciter and sin/cos coils
Equation 11. GUID-D9C2AF92-01D8-4A04-AA13-9A3408048BB0-low.gif

where

  • Gdesired= gain setting for the system
  • VAMP_OUTx= differential amplitude between OUTxP and OUTxN
  • VAMP_INx= differential voltage on the INx pin

Keep the single-ended OUTx voltages within 10% to 90% of VREG. This example use a differential amplitude of 2.0 V.

When the desired gain is known, the voltage to apply to the AGC_EN pin can be calculated by rearranging Equation 7.

Equation 12. GUID-C3C0EF1A-5E9C-497D-8DA9-C95D2206B321-low.gif
Equation 13. GUID-A7C779D0-1D0F-4703-8D70-1753FA2A6603-low.gif

From there, the pullup and pulldown resistors can be calculated to achieve %VREGDesired. Make sure there are 0.1% tolerant resistors and that the loading does not violate the ILOAD_REG_EXT specification.

Choose R2 = 10 kΩ

Equation 14. GUID-4C1E7318-E728-4B6A-9F92-8E893B2CB3A0-low.gif

Finally, choose the closest resistor value and make sure that the final gain will be within the acceptable limits. In this case, choose R1 = 16.0 kΩ.