JAJSDB3 June   2017 LF298-MIL

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
    2. 7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
    3. 7.3 Operational Amplifier Drive
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Hold Capacitor
      2. 9.1.2 DC and AC Zeroing
      3. 9.1.3 Logic Rise Time
      4. 9.1.4 Sampling Dynamic Signals
      5. 9.1.5 Digital Feedthrough
    2. 9.2 Typical Applications
      1. 9.2.1  X1000 Sample and Hold
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2  Sample and Difference Circuit
      3. 9.2.3  Ramp Generator With Variable Reset Level
      4. 9.2.4  Integrator With Programmable Reset Level
      5. 9.2.5  Output Holds at Average of Sampled Input
      6. 9.2.6  Increased Slew Current
      7. 9.2.7  Reset Stabilized Amplifier
      8. 9.2.8  Fast Acquisition, Low Droop Sample and Hold
      9. 9.2.9  Synchronous Correlator for Recovering Signals Below Noise Level
      10. 9.2.10 2-Channel Switch
      11. 9.2.11 DC and AC Zeroing
      12. 9.2.12 Staircase Generator
      13. 9.2.13 Differential Hold
      14. 9.2.14 Capacitor Hysteresis Compensation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and ground. A ground plane underneath the device is recommended; any bypass components to ground should have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the power supply inductance and provide a more stable power supply. The feedback components should be placed as close to the device as possible to minimize stray parasitics.

11.2 Layout Example

Figure 41 shows an example schematic and layout for the LF298-MIL 8-pin PDIP package.

LF298-MIL soic_schematic_snosbi3.gif Figure 41. Schematic Example
LF298-MIL soic_layout_snosbi3.png Figure 42. Layout Example