JAJSDB3
June 2017
LF298-MIL
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
4
改訂履歴
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Recommended Operating Conditions
6.3
Thermal Information
6.4
Electrical Characteristics
6.5
Typical Characteristics
7
Parameter Measurement Information
7.1
TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
7.2
CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
7.3
Operational Amplifier Drive
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Hold Capacitor
9.1.2
DC and AC Zeroing
9.1.3
Logic Rise Time
9.1.4
Sampling Dynamic Signals
9.1.5
Digital Feedthrough
9.2
Typical Applications
9.2.1
X1000 Sample and Hold
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Sample and Difference Circuit
9.2.3
Ramp Generator With Variable Reset Level
9.2.4
Integrator With Programmable Reset Level
9.2.5
Output Holds at Average of Sampled Input
9.2.6
Increased Slew Current
9.2.7
Reset Stabilized Amplifier
9.2.8
Fast Acquisition, Low Droop Sample and Hold
9.2.9
Synchronous Correlator for Recovering Signals Below Noise Level
9.2.10
2-Channel Switch
9.2.11
DC and AC Zeroing
9.2.12
Staircase Generator
9.2.13
Differential Hold
9.2.14
Capacitor Hysteresis Compensation
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
デバイスの項目表記
12.2
ドキュメントの更新通知を受け取る方法
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
LMC|8
MMBC008A
サーマルパッド・メカニカル・データ
発注情報
jajsdb3_oa
7
Parameter Measurement Information
7.1
TTL and CMOS 3 V ≤ V
LOGIC
(Hi State) ≤ 7 V
Threshold = 1.4 V
Figure 18.
Sample When Logic High With TTL and CMOS Biasing
Threshold = 1.4 V
Select for 2.8 V at pin 8
Figure 19.
Sample When Logic Low With TTL and CMOS Biasing
7.2
CMOS 7 V ≤ V
LOGIC
(Hi State) ≤ 15 V
Threshold = 0.6 (V
+
) + 1.4 V
Figure 20.
Sample When Logic High With CMOS Biasing
Threshold = 0.6 (V
+
) –1.4V
Figure 21.
Sample When Logic Low With CMOS Biasing
7.3
Operational Amplifier Drive
Threshold ≈ +4 V
Figure 22.
Sample When Logic High With Operational Amplifier Biasing
Threshold = −4 V
Figure 23.
Sample When Logic Low With Operational Amplifier Biasing