JAJSB70C
July 2000 – October 2018
LF198-N
,
LF298
,
LF398-N
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的な接続
アクイジション時間
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Recommended Operating Conditions
7.3
Thermal Information
7.4
Electrical Characteristics, LF198-N and LF298
7.5
Electrical Characteristics, LF198A-N
7.6
Electrical Characteristics, LF398-N
7.7
Electrical Characteristics, LF398A-N (OBSOLETE)
7.8
Typical Characteristics
8
Parameter Measurement Information
8.1
TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
8.2
CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
8.3
Operational Amplifier Drive
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.4
Device Functional Modes
10
Application and Implementation
10.1
Application Information
10.1.1
Hold Capacitor
10.1.2
DC and AC Zeroing
10.1.3
Logic Rise Time
10.1.4
Sampling Dynamic Signals
10.1.5
Digital Feedthrough
10.2
Typical Applications
10.2.1
X1000 Sample and Hold
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
Sample and Difference Circuit
10.2.3
Ramp Generator With Variable Reset Level
10.2.4
Integrator With Programmable Reset Level
10.2.5
Output Holds at Average of Sampled Input
10.2.6
Increased Slew Current
10.2.7
Reset Stabilized Amplifier
10.2.8
Fast Acquisition, Low Droop Sample and Hold
10.2.9
Synchronous Correlator for Recovering Signals Below Noise Level
10.2.10
2-Channel Switch
10.2.11
DC and AC Zeroing
10.2.12
Staircase Generator
10.2.13
Differential Hold
10.2.14
Capacitor Hysteresis Compensation
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
デバイス・サポート
13.1.1
デバイスの項目表記
13.2
関連リンク
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|14
MPDS177H
サーマルパッド・メカニカル・データ
発注情報
jajsb70c_oa
jajsb70c_pm
7.8
Typical Characteristics
Figure 1.
Aperture Time
Figure 3.
Dynamic Sampling Error
Figure 5.
Hold Step
Figure 7.
Leakage Current into Hold Capacitor
Figure 9.
Gain Error
Figure 11.
Output Short Circuit Current
Figure 13.
Input Bias Current
Figure 15.
Hold Step vs Input Voltage
Figure 17.
Output Transient at Start of Hold Mode
Figure 2.
Dielectric Absorption Error in Hold Capacitor
Figure 4.
Output Droop Rate
Figure 6.
Hold Settling Time
Figure 8.
Phase and Gain (Input to Output, Small Signal)
Figure 10.
Power Supply Rejection
Figure 12.
Output Noise
Figure 14.
Feedthrough Rejection Ratio (Hold Mode)
Figure 16.
Output Transient at Start of Sample Mode