SNVS739F December   2011  – October 2016 LM10504

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - General
    6. 6.6  Electrical Characteristics - Buck 1
    7. 6.7  Electrical Characteristics - Buck 2
    8. 6.8  Electrical Characteristics - Buck 3
    9. 6.9  Electrical Characteristics - LDO
    10. 6.10 Electrical Characteristics - Comparators
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Regulators Description
      2. 7.3.2 PWM Operation
      3. 7.3.3 PFM Operation
      4. 7.3.4 Soft Start
      5. 7.3.5 Current Limiting
      6. 7.3.6 Internal Synchronous Rectification
      7. 7.3.7 Bypass-FET Operation on Buck 1 and Buck 2
      8. 7.3.8 Low Dropout Operation
      9. 7.3.9 Out of Regulation
    4. 7.4 Device Functional Modes
      1. 7.4.1  Start-Up Sequence
      2. 7.4.2  Power-On Default and Device Enable
      3. 7.4.3  Reset Pin Function
      4. 7.4.4  DevSLP Function
        1. 7.4.4.1 DevSLP Pin
        2. 7.4.4.2 DevSLP Programming Through SPI
        3. 7.4.4.3 DevSLP Operational Constraints
      5. 7.4.5  Vselect_B2, Vselect_B3 Function
      6. 7.4.6  Undervoltage Lockout (UVLO)
      7. 7.4.7  Overvoltage Lockout (OVLO)
      8. 7.4.8  Device Status, Interrupt Enable
      9. 7.4.9  Thermal Shutdown (TSD)
      10. 7.4.10 Comparator
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Components Selection
          1. 8.2.2.1.1 Output Inductors and Capacitors Selection
          2. 8.2.2.1.2 Inductor Selection
            1. 8.2.2.1.2.1 Recommended Method for Inductor Selection
            2. 8.2.2.1.2.2 Alternate Method for Inductor Selection
              1. 8.2.2.1.2.2.1 Suggested Inductors and Their Suppliers
          3. 8.2.2.1.3 Output and Input Capacitors Characteristics
            1. 8.2.2.1.3.1 Output Capacitor Selection
            2. 8.2.2.1.3.2 Input Capacitor Selection
        2. 8.2.2.2 Recommendations For Unused Functions and Pins
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Thermal Dissipation For DSGBA Package
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

YFR Package
34-Pin DSBGA
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
A1 Interrupt O Digital output of comparator to signal interrupt condition.
A2 LDO P LDO regulator output voltage.
A3 VIN P Power supply input voltage. Must be present for device to work; decouple closely to D7.
A4, B4 FB_B1 I/O Buck switcher regulator 1: Voltage output feedback plus bypass power.
A5, B5 VIN_B1 P Buck switcher regulator 1: Power supply voltage input for power stage PFET, if Buck 1 is not used, tie to ground to reduce leakage.
A6, B6 SW_B1 P Buck switcher regulator 1: Power switching node, connect to inductor.
A7, B7 GND_B1 P Buck switcher regulator 1: Power ground for buck regulator.
B1 VIN_IO I Supply voltage for digital interface.
B2 GND G Connect to system ground.
B3 GND G Connect to system ground.
C1 SPI_CLK I SPI interface: Serial clock input.
C7 VCOMP I Analog input for comparator.
D1 SPI_DI I SPI interface: Serial data input.
D7 GND G Connect to system ground; decouple closely to A3.
E1 SPI_DO O SPI interface: Serial data output.
E7 DevSLP I Digital input control signal for entering device sleep mode. This is an active high pin with an internal pulldown resistor. Lowers core ASIC voltage and turns off the FLASH and I/O bucks.
F1 SPI_CS I SPI interface: Chip select.
F2, G2 SW_B2 P Buck switcher regulator 2: Power switching node, connect to inductor.
F3 FB_B2 I Buck switcher regulator 2: Voltage output feedback.
F4 Vselect_B3 I Digital input start-up control signal to change predefined output voltage of buck 3, internally pulled up as a default.
F5 FB_B3 I Buck switcher regulator 3: Voltage output feedback.
F6, G6 SW_B3 P Buck switcher regulator 3: Power switching node, connect to inductor.
F7 RESET I Digital input control signal to abort SPI transactions; resets the PMIC to default voltages. This is an active low pin with an internal pullup.
G1 GND_B2 P Buck switcher regulator 2: Power ground for buck regulator.
G3 VIN_B2 P Buck switcher regulator 2: Power supply voltage input for power stage PFET, if buck 2 is not used, tie to ground to reduce leakage.
G4 Vselect_B2 I Digital input start-up control signal to change predefined output voltage of buck 2, internally pulled down as a default.
G5 VIN_B3 P Buck switcher regulator 3: Power supply voltage input for power stage PFET.
G7 GND_B3 P Buck switcher regulator 3: Power ground for buck regulator.
(1) G = Ground, I = Input, O = Output, and P = Power