SNVS729F September   2011  – August 2014 LM10506

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Buck 1 Electrical Characteristics
    7. 7.7  Buck 2 Electrical Characteristics
    8. 7.8  Buck 3 Electrical Characteristics
    9. 7.9  LDO Electrical Characteristics
    10. 7.10 Comparators Electrical Characteristics
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Buck Regulators Operation
        1. 8.2.1.1 Buck Regulators Description
        2. 8.2.1.2 PWM Operation
        3. 8.2.1.3 PFM Operation (Bucks 1, 2 & 3)
        4. 8.2.1.4 Soft Start
        5. 8.2.1.5 Current Limiting
        6. 8.2.1.6 Internal Synchronous Rectification
        7. 8.2.1.7 Bypass FET Operation On Bucks 1 And 2
        8. 8.2.1.8 Low Dropout Operation
        9. 8.2.1.9 Out of Regulation
    3. 8.3 Device Functional Modes
      1. 8.3.1  Start-Up Sequence
      2. 8.3.2  Power-On Default And Device Enable
      3. 8.3.3  RESET Pin Function
      4. 8.3.4  Standby Function
        1. 8.3.4.1 STANDBY Pin
        2. 8.3.4.2 Standby Programming Via SPI
        3. 8.3.4.3 Standby Mode, Operational Constraints
      5. 8.3.5  HL_B2, HL_B3 Function
      6. 8.3.6  Undervoltage Lockout (UVLO)
      7. 8.3.7  Overvoltage Lockout (OVLO)
      8. 8.3.8  Interrupt Enable/Interrupt Status
      9. 8.3.9  Thermal Shutdown (TSD)
      10. 8.3.10 Comparator
    4. 8.4 Programming
      1. 8.4.1 SPI Data Interface
        1. 8.4.1.1 Registers Configurable via the SPI Interface
          1. 8.4.1.1.1 ADDR 0x07& 0x08: Buck 1 And Buck 2 Voltage Code And VOUT Level Mapping
          2. 8.4.1.1.2 ADDR 0x00 & 0x09: Buck 3 Voltage Code And VOUT Level Mapping
          3. 8.4.1.1.3 ADDR0x0B: Comparator Threshold Mapping
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Voltage
        2. 9.2.2.2 Standby Mode
        3. 9.2.2.3 External Components Selection
          1. 9.2.2.3.1 Output Inductors & Capacitors Selection
          2. 9.2.2.3.2 Inductor Selection
            1. 9.2.2.3.2.1 Recommended Method For Inductor Selection:
            2. 9.2.2.3.2.2 Alternate Method For Inductor Selection:
              1. 9.2.2.3.2.2.1 Suggested Inductors and Their Suppliers
            3. 9.2.2.3.2.3 Output And Input Capacitors Characteristics
              1. 9.2.2.3.2.3.1 Output Capacitor Selection
              2. 9.2.2.3.2.3.2 Input Capacitor Selection
        4. 9.2.2.4 Recommendations For Unused Functions And Pins
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations
      2. 11.1.2 PCB Layout Thermal Dissipation For DSBGA Package
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Considerations

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

30166225.gifSchematic Of LM10506 Highlighting Layout Sensitive Nodes
  1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched rapidly. The first loop starts from the CIN input capacitor, to the regulator SWx_VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor COUT and load. The second loop starts from the output capacitor ground, to the regulator SWx_GND pins, to the inductor and then out to COUT and the load (see above). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitors should consist of a small localized top side plane that connects to PGND. The inductor should be placed as close as possible to the SW pin and output capacitor.
  2. Minimize the copper area of the switch node. The SW pins should be directly connected with a trace that runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause too much capacitive loading on the SW pin. The inductors should be placed as close as possible to the SW pins to further minimize the copper area of the switch node.
  3. Have a single point ground for all device analog grounds. The ground connections for the feedback components should be connected together then routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior.
  4. Minimize trace length to the FB pin. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise.
  5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy.

Outside 7x7 array 0.4 mm 34-bump DSBGA, with 24 peripheral and 6 inner vias = 30 individual signals

11.1.2 PCB Layout Thermal Dissipation For DSBGA Package

  1. Position ground layer as close as possible to DSBGA package. Second PCB layer is usually good option. LM10506 evaluation board is a good example.
  2. Draw power traces as wide as possible. Bumps which carry high currents should be connected to wide traces. This helps the silicon to cool down.

11.2 Layout Example

30166226.pngFigure 29. Possible PCB Layout Configuration
6x Through Hole Vias In The Middle