JAJSBH5B March   2011  – June 2019 LM21212-2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーションの簡略回路図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Ratings
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Enable
      2. 8.3.2 UVLO
      3. 8.3.3 Current Limit
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Protection
      6. 8.3.6 Power-Good Flag
      7. 8.3.7 Light Load Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage
          3. 9.2.1.2.3 Precision Enable
          4. 9.2.1.2.4 Soft Start
          5. 9.2.1.2.5 Resistor-Adjustable Frequency
          6. 9.2.1.2.6 Inductor Selection
          7. 9.2.1.2.7 Output Capacitor Selection
          8. 9.2.1.2.8 Input Capacitor Selection
          9. 9.2.1.2.9 Control Loop Compensation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application Schematic 2
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Layout
    1. 10.1 Layout Considerations
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25°C only, limits in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM
VFB Feedback pin voltage VIN = 2.95V to 5.5V -1% 0.6 1% V
ΔVOUT/ΔIOUT Load Regulation 0.02 %VOUT/A
ΔVOUT/ΔVIN Line Regulation 0.1 %VOUT/V
RDSON HS High Side Switch On Resistance ISW = 12A 7.0 9.0 mΩ
RDSON LS Low Side Switch On Resistance ISW = 12A 4.3 6.0 mΩ
ICLR HS Rising Switch Current Limit 15 17 19 A
ICLF LS Falling Switch Current Limit 12 A
VZX Zero Cross Voltage -8 3 12 mV
IQ Operating Quiescent Current 1.5 3.0 mA
ISD Shutdown Quiescent Current VEN = 0V 50 70 µA
VUVLO AVIN Undervoltage Lockout AVIN Rising 2.45 2.70 2.95 V
VUVLOHYS AVIN Undervoltage Lockout Hysteresis 140 200 280 mV
VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) 0 < VTRACK < 0.55V -10 6 20 mV
ISS Soft-Start Pin Source Current 1.3 1.9 2.5 µA
tINTSS Internal Soft-Start Ramp to Vref CSS = 0 350 500 675 µs
tRESETSS Device Reset to Soft-Start Ramp 50 110 200 µs
OSCILLATOR
fRNG FADJ Frequency Range 300 1550 kHz
fSW Switching Frequency RADJ = 22.6kΩ 1400 1550 1700 kHz
RADJ = 95.3kΩ 465 500 535
tHSBLANK HS OCP Blanking Time Rising edge of SW to ICLR comparison 55 ns
tLSBLANK LS OCP Blanking Time Falling edge of SW to ICLF comparison 400 ns
tZXBLANK Zero Cross Blanking Time Falling edge of SW to VZX comparison 120 ns
tMINON Minimum HS on-time 140 ns
ΔVramp PWM Ramp p-p Voltage 0.8 V
ERROR AMPLIFIER
VOL Error Amplifier Open Loop Voltage Gain ICOMP = -65µA to 1mA 95 dBV/V
GBW Error Amplifier Gain-Bandwidth Product 11 MHz
IFB Feedback Pin Bias Current VFB = 0.6V 1 nA
ICOMPSRC COMP Output Source Current 1 mA
ICOMPSINK COMP Output Sink Current 65 µA
POWERGOOD
VOVP Overvoltage Protection Rising Threshold VFB Rising 105 112.5 120 %VFB
VOVPHYS Overvoltage Protection Hysteresis VFB Falling 2 %VFB
VUVP Undervoltage Protection Rising Threshold VFB Rising 82 90 97 %VFB
VUVPHYS Undervoltage Protection Hysteresis VFB Falling 2.5 %VFB
tPGDGL PGOOD Deglitch Low (OVP/UVP Condition Duration to PGOOD Falling) 15 µs
tPGDGH PGOOD Deglitch High (minimum low pulse) 12 µs
RPGOOD PGOOD Pulldown Resistance 10 20 40 Ω
IPGOODLEAK PGOOD Leakage Current VPGOOD = 5V 1 nA
LOGIC
VIHSYNC SYNC Pin Logic High 2.0 V
VILSYNC SYNC Pin Logic Low 0.8 V
VIHENR EN Pin Rising Threshold VEN Rising 1.20 1.35 1.45 V
VENHYS EN Pin Hysteresis 50 110 180 mV
IEN EN Pin Pullup Current VEN = 0V 2 µA
THERMAL SHUTDOWN
TTHERMSD Thermal Shutdown 165 °C
TTHERMSDHYS Thermal Shutdown Hysteresis 10 °C